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34 lines
976 B
Text
34 lines
976 B
Text
read_verilog ../../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic -family qlf_k6n10f
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:latchsre
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select -assert-none t:latchsre %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic -family qlf_k6n10f
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:latchnsre
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select -assert-none t:latchnsre %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic -family qlf_k6n10f
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 2 t:$lut
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select -assert-count 1 t:dffsr
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select -assert-none t:$lut t:dffsr %% t:* %D
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