read_verilog ../../common/latches.v
design -save read

hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -family qlf_k6n10f
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:latchsre

select -assert-none t:latchsre %% t:* %D


design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -family qlf_k6n10f
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:latchnsre

select -assert-none t:latchnsre %% t:* %D


design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -family qlf_k6n10f
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:$lut
select -assert-count 1 t:dffsr

select -assert-none t:$lut t:dffsr %% t:* %D