mirror of
https://github.com/YosysHQ/yosys
synced 2026-02-07 17:48:00 +00:00
2033 lines
61 KiB
Verilog
2033 lines
61 KiB
Verilog
// Created by cells_xtra.py from Lattice models
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(* blackbox *) (* keep *)
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module GSR(GSR);
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input GSR;
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endmodule
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(* blackbox *)
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module PUR(PUR);
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parameter RST_PULSE = 1;
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input PUR;
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endmodule
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(* blackbox *) (* keep *)
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module SGSR(GSR, CLK);
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input GSR;
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input CLK;
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endmodule
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(* blackbox *)
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module PDPW16KD(DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, DI17, DI16, DI15
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, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6, ADW5, ADW4, ADW3
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, ADW2, ADW1, ADW0, BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
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, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27
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, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6
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, DO5, DO4, DO3, DO2, DO1, DO0);
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parameter CLKRMUX = "CLKR";
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parameter CLKWMUX = "CLKW";
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parameter DATA_WIDTH_W = 36;
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parameter DATA_WIDTH_R = 36;
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parameter GSR = "ENABLED";
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parameter REGMODE = "NOREG";
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parameter RESETMODE = "SYNC";
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parameter ASYNC_RESET_RELEASE = "SYNC";
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parameter CSDECODE_W = "0b000";
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parameter CSDECODE_R = "0b000";
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parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_DATA = "STATIC";
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input DI35;
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input DI34;
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input DI33;
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input DI32;
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input DI31;
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input DI30;
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input DI29;
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input DI28;
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input DI27;
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input DI26;
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input DI25;
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input DI24;
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input DI23;
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input DI22;
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input DI21;
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input DI20;
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input DI19;
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input DI18;
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input DI17;
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input DI16;
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input DI15;
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input DI14;
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input DI13;
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input DI12;
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input DI11;
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input DI10;
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input DI9;
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input DI8;
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input DI7;
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input DI6;
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input DI5;
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input DI4;
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input DI3;
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input DI2;
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input DI1;
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input DI0;
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input ADW8;
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input ADW7;
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input ADW6;
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input ADW5;
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input ADW4;
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input ADW3;
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input ADW2;
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input ADW1;
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input ADW0;
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input BE3;
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input BE2;
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input BE1;
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input BE0;
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input CEW;
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input CLKW;
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input CSW2;
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input CSW1;
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input CSW0;
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input ADR13;
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input ADR12;
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input ADR11;
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input ADR10;
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input ADR9;
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input ADR8;
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input ADR7;
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input ADR6;
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input ADR5;
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input ADR4;
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input ADR3;
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input ADR2;
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input ADR1;
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input ADR0;
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input CER;
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input OCER;
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input CLKR;
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input CSR2;
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input CSR1;
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input CSR0;
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input RST;
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output DO35;
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output DO34;
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output DO33;
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output DO32;
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output DO31;
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output DO30;
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output DO29;
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output DO28;
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output DO27;
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output DO26;
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output DO25;
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output DO24;
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output DO23;
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output DO22;
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output DO21;
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output DO20;
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output DO19;
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output DO18;
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output DO17;
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output DO16;
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output DO15;
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output DO14;
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output DO13;
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output DO12;
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output DO11;
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output DO10;
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output DO9;
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output DO8;
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output DO7;
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output DO6;
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output DO5;
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output DO4;
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output DO3;
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output DO2;
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output DO1;
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output DO0;
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endmodule
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(* blackbox *)
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module MULT18X18D(A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0, B17, B16, B15
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, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0, C17, C16, C15, C14, C13, C12
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, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, CLK3, CLK2, CLK1, CLK0, CE3
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, CE2, CE1, CE0, RST3, RST2, RST1, RST0, SRIA17, SRIA16, SRIA15, SRIA14, SRIA13, SRIA12, SRIA11, SRIA10, SRIA9, SRIA8, SRIA7, SRIA6, SRIA5, SRIA4
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, SRIA3, SRIA2, SRIA1, SRIA0, SRIB17, SRIB16, SRIB15, SRIB14, SRIB13, SRIB12, SRIB11, SRIB10, SRIB9, SRIB8, SRIB7, SRIB6, SRIB5, SRIB4, SRIB3, SRIB2, SRIB1
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, SRIB0, SROA17, SROA16, SROA15, SROA14, SROA13, SROA12, SROA11, SROA10, SROA9, SROA8, SROA7, SROA6, SROA5, SROA4, SROA3, SROA2, SROA1, SROA0, SROB17, SROB16
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, SROB15, SROB14, SROB13, SROB12, SROB11, SROB10, SROB9, SROB8, SROB7, SROB6, SROB5, SROB4, SROB3, SROB2, SROB1, SROB0, ROA17, ROA16, ROA15, ROA14, ROA13
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, ROA12, ROA11, ROA10, ROA9, ROA8, ROA7, ROA6, ROA5, ROA4, ROA3, ROA2, ROA1, ROA0, ROB17, ROB16, ROB15, ROB14, ROB13, ROB12, ROB11, ROB10
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, ROB9, ROB8, ROB7, ROB6, ROB5, ROB4, ROB3, ROB2, ROB1, ROB0, ROC17, ROC16, ROC15, ROC14, ROC13, ROC12, ROC11, ROC10, ROC9, ROC8, ROC7
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, ROC6, ROC5, ROC4, ROC3, ROC2, ROC1, ROC0, P35, P34, P33, P32, P31, P30, P29, P28, P27, P26, P25, P24, P23, P22
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, P21, P20, P19, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, P7, P6, P5, P4, P3, P2, P1
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, P0, SIGNEDP);
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parameter REG_INPUTA_CLK = "NONE";
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parameter REG_INPUTA_CE = "CE0";
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parameter REG_INPUTA_RST = "RST0";
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parameter REG_INPUTB_CLK = "NONE";
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parameter REG_INPUTB_CE = "CE0";
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parameter REG_INPUTB_RST = "RST0";
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parameter REG_INPUTC_CLK = "NONE";
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parameter REG_INPUTC_CE = "CE0";
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parameter REG_INPUTC_RST = "RST0";
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parameter REG_PIPELINE_CLK = "NONE";
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parameter REG_PIPELINE_CE = "CE0";
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parameter REG_PIPELINE_RST = "RST0";
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parameter REG_OUTPUT_CLK = "NONE";
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parameter REG_OUTPUT_CE = "CE0";
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parameter REG_OUTPUT_RST = "RST0";
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parameter CLK0_DIV = "ENABLED";
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parameter CLK1_DIV = "ENABLED";
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parameter CLK2_DIV = "ENABLED";
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parameter CLK3_DIV = "ENABLED";
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parameter HIGHSPEED_CLK = "NONE";
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parameter GSR = "ENABLED";
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parameter CAS_MATCH_REG = "FALSE";
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parameter SOURCEB_MODE = "B_SHIFT";
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parameter MULT_BYPASS = "DISABLED";
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parameter RESETMODE = "SYNC";
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input A17;
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input A16;
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input A15;
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input A14;
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input A13;
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input A12;
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input A11;
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input A10;
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input A9;
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input A8;
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input A7;
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input A6;
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input A5;
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input A4;
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input A3;
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input A2;
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input A1;
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input A0;
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input B17;
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input B16;
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input B15;
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input B14;
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input B13;
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input B12;
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input B11;
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input B10;
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input B9;
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input B8;
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input B7;
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input B6;
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input B5;
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input B4;
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input B3;
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input B2;
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input B1;
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input B0;
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input C17;
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input C16;
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input C15;
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input C14;
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input C13;
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input C12;
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input C11;
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input C10;
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input C9;
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input C8;
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input C7;
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input C6;
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input C5;
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input C4;
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input C3;
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input C2;
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input C1;
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input C0;
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input SIGNEDA;
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input SIGNEDB;
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input SOURCEA;
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input SOURCEB;
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input CLK3;
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input CLK2;
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input CLK1;
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input CLK0;
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input CE3;
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input CE2;
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input CE1;
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input CE0;
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input RST3;
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input RST2;
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input RST1;
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input RST0;
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input SRIA17;
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input SRIA16;
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input SRIA15;
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input SRIA14;
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input SRIA13;
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input SRIA12;
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input SRIA11;
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input SRIA10;
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input SRIA9;
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input SRIA8;
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input SRIA7;
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input SRIA6;
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input SRIA5;
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input SRIA4;
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input SRIA3;
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input SRIA2;
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input SRIA1;
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input SRIA0;
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input SRIB17;
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input SRIB16;
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input SRIB15;
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input SRIB14;
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input SRIB13;
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input SRIB12;
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input SRIB11;
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input SRIB10;
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input SRIB9;
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input SRIB8;
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input SRIB7;
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input SRIB6;
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input SRIB5;
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input SRIB4;
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input SRIB3;
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input SRIB2;
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input SRIB1;
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input SRIB0;
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output SROA17;
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output SROA16;
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output SROA15;
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output SROA14;
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output SROA13;
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output SROA12;
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output SROA11;
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output SROA10;
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output SROA9;
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output SROA8;
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output SROA7;
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output SROA6;
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output SROA5;
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output SROA4;
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output SROA3;
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output SROA2;
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output SROA1;
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output SROA0;
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output SROB17;
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output SROB16;
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output SROB15;
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output SROB14;
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output SROB13;
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output SROB12;
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output SROB11;
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output SROB10;
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output SROB9;
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output SROB8;
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output SROB7;
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output SROB6;
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output SROB5;
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output SROB4;
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output SROB3;
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output SROB2;
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output SROB1;
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output SROB0;
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output ROA17;
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output ROA16;
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output ROA15;
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output ROA14;
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output ROA13;
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output ROA12;
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output ROA11;
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output ROA10;
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output ROA9;
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output ROA8;
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output ROA7;
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output ROA6;
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output ROA5;
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output ROA4;
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output ROA3;
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output ROA2;
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output ROA1;
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output ROA0;
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output ROB17;
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output ROB16;
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output ROB15;
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output ROB14;
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output ROB13;
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output ROB12;
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output ROB11;
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output ROB10;
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output ROB9;
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output ROB8;
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output ROB7;
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output ROB6;
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output ROB5;
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output ROB4;
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output ROB3;
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output ROB2;
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output ROB1;
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output ROB0;
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output ROC17;
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output ROC16;
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output ROC15;
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output ROC14;
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output ROC13;
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output ROC12;
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output ROC11;
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output ROC10;
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output ROC9;
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output ROC8;
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output ROC7;
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output ROC6;
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output ROC5;
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output ROC4;
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output ROC3;
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output ROC2;
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output ROC1;
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output ROC0;
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output P35;
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output P34;
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output P33;
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output P32;
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output P31;
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output P30;
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output P29;
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output P28;
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output P27;
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output P26;
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output P25;
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output P24;
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output P23;
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output P22;
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output P21;
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output P20;
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output P19;
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output P18;
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output P17;
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output P16;
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output P15;
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output P14;
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output P13;
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output P12;
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output P11;
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output P10;
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output P9;
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output P8;
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output P7;
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output P6;
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output P5;
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output P4;
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output P3;
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output P2;
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output P1;
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output P0;
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output SIGNEDP;
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endmodule
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|
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(* blackbox *)
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module ALU54B(CE3, CE2, CE1, CE0, CLK3, CLK2, CLK1, CLK0, RST3, RST2, RST1, RST0, SIGNEDIA, SIGNEDIB, SIGNEDCIN, A35, A34, A33, A32, A31, A30
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, A29, A28, A27, A26, A25, A24, A23, A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9
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, A8, A7, A6, A5, A4, A3, A2, A1, A0, B35, B34, B33, B32, B31, B30, B29, B28, B27, B26, B25, B24
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, B23, B22, B21, B20, B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3
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, B2, B1, B0, C53, C52, C51, C50, C49, C48, C47, C46, C45, C44, C43, C42, C41, C40, C39, C38, C37, C36
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, C35, C34, C33, C32, C31, C30, C29, C28, C27, C26, C25, C24, C23, C22, C21, C20, C19, C18, C17, C16, C15
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, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, CFB53, CFB52, CFB51, CFB50, CFB49, CFB48
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, CFB47, CFB46, CFB45, CFB44, CFB43, CFB42, CFB41, CFB40, CFB39, CFB38, CFB37, CFB36, CFB35, CFB34, CFB33, CFB32, CFB31, CFB30, CFB29, CFB28, CFB27
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, CFB26, CFB25, CFB24, CFB23, CFB22, CFB21, CFB20, CFB19, CFB18, CFB17, CFB16, CFB15, CFB14, CFB13, CFB12, CFB11, CFB10, CFB9, CFB8, CFB7, CFB6
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, CFB5, CFB4, CFB3, CFB2, CFB1, CFB0, MA35, MA34, MA33, MA32, MA31, MA30, MA29, MA28, MA27, MA26, MA25, MA24, MA23, MA22, MA21
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, MA20, MA19, MA18, MA17, MA16, MA15, MA14, MA13, MA12, MA11, MA10, MA9, MA8, MA7, MA6, MA5, MA4, MA3, MA2, MA1, MA0
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, MB35, MB34, MB33, MB32, MB31, MB30, MB29, MB28, MB27, MB26, MB25, MB24, MB23, MB22, MB21, MB20, MB19, MB18, MB17, MB16, MB15
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, MB14, MB13, MB12, MB11, MB10, MB9, MB8, MB7, MB6, MB5, MB4, MB3, MB2, MB1, MB0, CIN53, CIN52, CIN51, CIN50, CIN49, CIN48
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, CIN47, CIN46, CIN45, CIN44, CIN43, CIN42, CIN41, CIN40, CIN39, CIN38, CIN37, CIN36, CIN35, CIN34, CIN33, CIN32, CIN31, CIN30, CIN29, CIN28, CIN27
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, CIN26, CIN25, CIN24, CIN23, CIN22, CIN21, CIN20, CIN19, CIN18, CIN17, CIN16, CIN15, CIN14, CIN13, CIN12, CIN11, CIN10, CIN9, CIN8, CIN7, CIN6
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, CIN5, CIN4, CIN3, CIN2, CIN1, CIN0, OP10, OP9, OP8, OP7, OP6, OP5, OP4, OP3, OP2, OP1, OP0, R53, R52, R51, R50
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, R49, R48, R47, R46, R45, R44, R43, R42, R41, R40, R39, R38, R37, R36, R35, R34, R33, R32, R31, R30, R29
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, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R16, R15, R14, R13, R12, R11, R10, R9, R8
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, R7, R6, R5, R4, R3, R2, R1, R0, CO53, CO52, CO51, CO50, CO49, CO48, CO47, CO46, CO45, CO44, CO43, CO42, CO41
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, CO40, CO39, CO38, CO37, CO36, CO35, CO34, CO33, CO32, CO31, CO30, CO29, CO28, CO27, CO26, CO25, CO24, CO23, CO22, CO21, CO20
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, CO19, CO18, CO17, CO16, CO15, CO14, CO13, CO12, CO11, CO10, CO9, CO8, CO7, CO6, CO5, CO4, CO3, CO2, CO1, CO0, EQZ
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, EQZM, EQOM, EQPAT, EQPATB, OVER, UNDER, OVERUNDER, SIGNEDR);
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parameter REG_INPUTC0_CLK = "NONE";
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parameter REG_INPUTC0_CE = "CE0";
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parameter REG_INPUTC0_RST = "RST0";
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parameter REG_INPUTC1_CLK = "NONE";
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parameter REG_INPUTC1_CE = "CE0";
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parameter REG_INPUTC1_RST = "RST0";
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parameter REG_OPCODEOP0_0_CLK = "NONE";
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parameter REG_OPCODEOP0_0_CE = "CE0";
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parameter REG_OPCODEOP0_0_RST = "RST0";
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parameter REG_OPCODEOP1_0_CLK = "NONE";
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parameter REG_OPCODEOP0_1_CLK = "NONE";
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parameter REG_OPCODEOP0_1_CE = "CE0";
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parameter REG_OPCODEOP0_1_RST = "RST0";
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parameter REG_OPCODEOP1_1_CLK = "NONE";
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parameter REG_OPCODEIN_0_CLK = "NONE";
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parameter REG_OPCODEIN_0_CE = "CE0";
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parameter REG_OPCODEIN_0_RST = "RST0";
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parameter REG_OPCODEIN_1_CLK = "NONE";
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parameter REG_OPCODEIN_1_CE = "CE0";
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parameter REG_OPCODEIN_1_RST = "RST0";
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parameter REG_OUTPUT0_CLK = "NONE";
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parameter REG_OUTPUT0_CE = "CE0";
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parameter REG_OUTPUT0_RST = "RST0";
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parameter REG_OUTPUT1_CLK = "NONE";
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parameter REG_OUTPUT1_CE = "CE0";
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parameter REG_OUTPUT1_RST = "RST0";
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parameter REG_FLAG_CLK = "NONE";
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parameter REG_FLAG_CE = "CE0";
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parameter REG_FLAG_RST = "RST0";
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parameter MCPAT_SOURCE = "STATIC";
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parameter MASKPAT_SOURCE = "STATIC";
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parameter MASK01 = "0x00000000000000";
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parameter REG_INPUTCFB_CLK = "NONE";
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parameter REG_INPUTCFB_CE = "CE0";
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parameter REG_INPUTCFB_RST = "RST0";
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parameter CLK0_DIV = "ENABLED";
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parameter CLK1_DIV = "ENABLED";
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parameter CLK2_DIV = "ENABLED";
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parameter CLK3_DIV = "ENABLED";
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parameter MCPAT = "0x00000000000000";
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parameter MASKPAT = "0x00000000000000";
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parameter RNDPAT = "0x00000000000000";
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parameter GSR = "ENABLED";
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parameter RESETMODE = "SYNC";
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parameter MULT9_MODE = "DISABLED";
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parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
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parameter LEGACY = "DISABLED";
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input CE3;
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input CE2;
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input CE1;
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input CE0;
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input CLK3;
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input CLK2;
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input CLK1;
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input CLK0;
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input RST3;
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input RST2;
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input RST1;
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input RST0;
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input SIGNEDIA;
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input SIGNEDIB;
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input SIGNEDCIN;
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input A35;
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input A34;
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input A33;
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input A32;
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input A31;
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input A30;
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input A29;
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input A28;
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input A27;
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input A26;
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input A25;
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input A24;
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input A23;
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input A22;
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input A21;
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input A20;
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input A19;
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input A18;
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input A17;
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input A16;
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input A15;
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input A14;
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input A13;
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input A12;
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input A11;
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input A10;
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input A9;
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input A8;
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input A7;
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input A6;
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input A5;
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input A4;
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input A3;
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input A2;
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input A1;
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input A0;
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input B35;
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input B34;
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input B33;
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input B32;
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input B31;
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input B30;
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input B29;
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input B28;
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input B27;
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input B26;
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input B25;
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input B24;
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input B23;
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input B22;
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input B21;
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input B20;
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input B19;
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input B18;
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input B17;
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input B16;
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input B15;
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input B14;
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input B13;
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input B12;
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input B11;
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input B10;
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input B9;
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input B8;
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input B7;
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input B6;
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input B5;
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input B4;
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input B3;
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input B2;
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input B1;
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input B0;
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input C53;
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input C52;
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input C51;
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input C50;
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input C49;
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input C48;
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input C47;
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input C46;
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input C45;
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input C44;
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input C43;
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input C42;
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input C41;
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input C40;
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input C39;
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input C38;
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input C37;
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input C36;
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input C35;
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input C34;
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input C33;
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input C32;
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input C31;
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input C30;
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input C29;
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input C28;
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input C27;
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input C26;
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input C25;
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input C24;
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input C23;
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input C22;
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input C21;
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input C20;
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input C19;
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input C18;
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input C17;
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input C16;
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input C15;
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input C14;
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input C13;
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input C12;
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input C11;
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input C10;
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input C9;
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input C8;
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input C7;
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input C6;
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input C5;
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input C4;
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input C3;
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input C2;
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input C1;
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input C0;
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input CFB53;
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input CFB52;
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input CFB51;
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input CFB50;
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input CFB49;
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input CFB48;
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input CFB47;
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input CFB46;
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input CFB45;
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input CFB44;
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input CFB43;
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input CFB42;
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input CFB41;
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input CFB40;
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input CFB39;
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input CFB38;
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input CFB37;
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input CFB36;
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input CFB35;
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input CFB34;
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input CFB33;
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input CFB32;
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input CFB31;
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input CFB30;
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input CFB29;
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input CFB28;
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input CFB27;
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input CFB26;
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input CFB25;
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input CFB24;
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input CFB23;
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input CFB22;
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input CFB21;
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input CFB20;
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input CFB19;
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input CFB18;
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input CFB17;
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input CFB16;
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input CFB15;
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input CFB14;
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input CFB13;
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input CFB12;
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input CFB11;
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input CFB10;
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input CFB9;
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input CFB8;
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input CFB7;
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input CFB6;
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input CFB5;
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input CFB4;
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input CFB3;
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input CFB2;
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input CFB1;
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input CFB0;
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input MA35;
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input MA34;
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input MA33;
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input MA32;
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input MA31;
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input MA30;
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input MA29;
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input MA28;
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input MA27;
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input MA26;
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input MA25;
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input MA24;
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input MA23;
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input MA22;
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input MA21;
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input MA20;
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input MA19;
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input MA18;
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input MA17;
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input MA16;
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input MA15;
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input MA14;
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input MA13;
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input MA12;
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input MA11;
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input MA10;
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input MA9;
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input MA8;
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input MA7;
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input MA6;
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input MA5;
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input MA4;
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input MA3;
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input MA2;
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input MA1;
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input MA0;
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input MB35;
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input MB34;
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input MB33;
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input MB32;
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input MB31;
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input MB30;
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input MB29;
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input MB28;
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input MB27;
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input MB26;
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input MB25;
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input MB24;
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input MB23;
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input MB22;
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input MB21;
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input MB20;
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input MB19;
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input MB18;
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input MB17;
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input MB16;
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input MB15;
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input MB14;
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input MB13;
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input MB12;
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input MB11;
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input MB10;
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input MB9;
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input MB8;
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input MB7;
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input MB6;
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input MB5;
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input MB4;
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input MB3;
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input MB2;
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input MB1;
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input MB0;
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input CIN53;
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input CIN52;
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input CIN51;
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input CIN50;
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input CIN49;
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input CIN48;
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input CIN47;
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input CIN46;
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input CIN45;
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input CIN44;
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input CIN43;
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input CIN42;
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input CIN41;
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input CIN40;
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input CIN39;
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input CIN38;
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input CIN37;
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input CIN36;
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input CIN35;
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input CIN34;
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input CIN33;
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input CIN32;
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input CIN31;
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input CIN30;
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input CIN29;
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input CIN28;
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input CIN27;
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input CIN26;
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input CIN25;
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input CIN24;
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input CIN23;
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input CIN22;
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input CIN21;
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input CIN20;
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input CIN19;
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input CIN18;
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input CIN17;
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input CIN16;
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input CIN15;
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input CIN14;
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input CIN13;
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input CIN12;
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input CIN11;
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input CIN10;
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input CIN9;
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input CIN8;
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input CIN7;
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input CIN6;
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input CIN5;
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input CIN4;
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input CIN3;
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input CIN2;
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input CIN1;
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input CIN0;
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input OP10;
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input OP9;
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input OP8;
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input OP7;
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input OP6;
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input OP5;
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input OP4;
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input OP3;
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input OP2;
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input OP1;
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input OP0;
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output R53;
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output R52;
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output R51;
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output R50;
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output R49;
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output R48;
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output R47;
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output R46;
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output R45;
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output R44;
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output R43;
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output R42;
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output R41;
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output R40;
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output R39;
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output R38;
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output R37;
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output R36;
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output R35;
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output R34;
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output R33;
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output R32;
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output R31;
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output R30;
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output R29;
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output R28;
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output R27;
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output R26;
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output R25;
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output R24;
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output R23;
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output R22;
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output R21;
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output R20;
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output R19;
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output R18;
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output R17;
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output R16;
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output R15;
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output R14;
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output R13;
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output R12;
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output R11;
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output R10;
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output R9;
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output R8;
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output R7;
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output R6;
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output R5;
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output R4;
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output R3;
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output R2;
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output R1;
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output R0;
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output CO53;
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output CO52;
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output CO51;
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output CO50;
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output CO49;
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output CO48;
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output CO47;
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output CO46;
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output CO45;
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output CO44;
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output CO43;
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output CO42;
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output CO41;
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output CO40;
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output CO39;
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output CO38;
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output CO37;
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output CO36;
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output CO35;
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output CO34;
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output CO33;
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output CO32;
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output CO31;
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output CO30;
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output CO29;
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output CO28;
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output CO27;
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output CO26;
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output CO25;
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output CO24;
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output CO23;
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output CO22;
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output CO21;
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output CO20;
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output CO19;
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output CO18;
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output CO17;
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output CO16;
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output CO15;
|
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output CO14;
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output CO13;
|
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output CO12;
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output CO11;
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output CO10;
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output CO9;
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output CO8;
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output CO7;
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output CO6;
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output CO5;
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output CO4;
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output CO3;
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output CO2;
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output CO1;
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output CO0;
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output EQZ;
|
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output EQZM;
|
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output EQOM;
|
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output EQPAT;
|
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output EQPATB;
|
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output OVER;
|
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output UNDER;
|
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output OVERUNDER;
|
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output SIGNEDR;
|
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endmodule
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|
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(* blackbox *)
|
|
module CLKDIVF(CLKI, RST, ALIGNWD, CDIVX);
|
|
parameter GSR = "DISABLED";
|
|
parameter DIV = "2.0";
|
|
input CLKI;
|
|
input RST;
|
|
input ALIGNWD;
|
|
output CDIVX;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module PCSCLKDIV(CLKI, RST, SEL2, SEL1, SEL0, CDIV1, CDIVX);
|
|
parameter GSR = "DISABLED";
|
|
input CLKI;
|
|
input RST;
|
|
input SEL2;
|
|
input SEL1;
|
|
input SEL0;
|
|
output CDIV1;
|
|
output CDIVX;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module DCSC(CLK1, CLK0, SEL1, SEL0, MODESEL, DCSOUT);
|
|
parameter DCSMODE = "POS";
|
|
input CLK1;
|
|
input CLK0;
|
|
input SEL1;
|
|
input SEL0;
|
|
input MODESEL;
|
|
output DCSOUT;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module DCCA(CLKI, CE, CLKO);
|
|
input CLKI;
|
|
input CE;
|
|
output CLKO;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module ECLKSYNCB(ECLKI, STOP, ECLKO);
|
|
input ECLKI;
|
|
input STOP;
|
|
output ECLKO;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
|
|
input CLK0;
|
|
input CLK1;
|
|
input SEL;
|
|
output ECSOUT;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module DELAYF(A, LOADN, MOVE, DIRECTION, Z, CFLAG);
|
|
parameter DEL_MODE = "USER_DEFINED";
|
|
parameter DEL_VALUE = 0;
|
|
input A;
|
|
input LOADN;
|
|
input MOVE;
|
|
input DIRECTION;
|
|
output Z;
|
|
output CFLAG;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module DELAYG(A, Z);
|
|
parameter DEL_MODE = "USER_DEFINED";
|
|
parameter DEL_VALUE = 0;
|
|
input A;
|
|
output Z;
|
|
endmodule
|
|
|
|
(* blackbox *) (* keep *)
|
|
module USRMCLK(USRMCLKI, USRMCLKTS);
|
|
input USRMCLKI;
|
|
input USRMCLKTS;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module DQSBUFM(DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL, ECLK, SCLK, RST, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, PAUSE, RDLOADN, RDMOVE
|
|
, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID, BURSTDET, RDCFLAG, WRCFLAG);
|
|
parameter DQS_LI_DEL_VAL = 4;
|
|
parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
|
|
parameter DQS_LO_DEL_VAL = 0;
|
|
parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
|
|
parameter GSR = "ENABLED";
|
|
input DQSI;
|
|
input READ1;
|
|
input READ0;
|
|
input READCLKSEL2;
|
|
input READCLKSEL1;
|
|
input READCLKSEL0;
|
|
input DDRDEL;
|
|
input ECLK;
|
|
input SCLK;
|
|
input RST;
|
|
input DYNDELAY7;
|
|
input DYNDELAY6;
|
|
input DYNDELAY5;
|
|
input DYNDELAY4;
|
|
input DYNDELAY3;
|
|
input DYNDELAY2;
|
|
input DYNDELAY1;
|
|
input DYNDELAY0;
|
|
input PAUSE;
|
|
input RDLOADN;
|
|
input RDMOVE;
|
|
input RDDIRECTION;
|
|
input WRLOADN;
|
|
input WRMOVE;
|
|
input WRDIRECTION;
|
|
output DQSR90;
|
|
output DQSW;
|
|
output DQSW270;
|
|
output RDPNTR2;
|
|
output RDPNTR1;
|
|
output RDPNTR0;
|
|
output WRPNTR2;
|
|
output WRPNTR1;
|
|
output WRPNTR0;
|
|
output DATAVALID;
|
|
output BURSTDET;
|
|
output RDCFLAG;
|
|
output WRCFLAG;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module DDRDLLA(CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0);
|
|
parameter FORCE_MAX_DELAY = "NO";
|
|
parameter GSR = "ENABLED";
|
|
input CLK;
|
|
input RST;
|
|
input UDDCNTLN;
|
|
input FREEZE;
|
|
output DDRDEL;
|
|
output LOCK;
|
|
output DCNTL7;
|
|
output DCNTL6;
|
|
output DCNTL5;
|
|
output DCNTL4;
|
|
output DCNTL3;
|
|
output DCNTL2;
|
|
output DCNTL1;
|
|
output DCNTL0;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module DLLDELD(A, DDRDEL, LOADN, MOVE, DIRECTION, Z, CFLAG);
|
|
input A;
|
|
input DDRDEL;
|
|
input LOADN;
|
|
input MOVE;
|
|
input DIRECTION;
|
|
output Z;
|
|
output CFLAG;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module IDDRX1F(D, SCLK, RST, Q0, Q1);
|
|
parameter GSR = "ENABLED";
|
|
input D;
|
|
input SCLK;
|
|
input RST;
|
|
output Q0;
|
|
output Q1;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module IDDRX2F(D, SCLK, ECLK, RST, ALIGNWD, Q3, Q2, Q1, Q0);
|
|
parameter GSR = "ENABLED";
|
|
input D;
|
|
input SCLK;
|
|
input ECLK;
|
|
input RST;
|
|
input ALIGNWD;
|
|
output Q3;
|
|
output Q2;
|
|
output Q1;
|
|
output Q0;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module IDDR71B(D, SCLK, ECLK, RST, ALIGNWD, Q6, Q5, Q4, Q3, Q2, Q1, Q0);
|
|
parameter GSR = "ENABLED";
|
|
input D;
|
|
input SCLK;
|
|
input ECLK;
|
|
input RST;
|
|
input ALIGNWD;
|
|
output Q6;
|
|
output Q5;
|
|
output Q4;
|
|
output Q3;
|
|
output Q2;
|
|
output Q1;
|
|
output Q0;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module IDDRX2DQA(SCLK, ECLK, DQSR90, D, RST, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, Q3, Q2, Q1, Q0, QWL);
|
|
parameter GSR = "ENABLED";
|
|
input SCLK;
|
|
input ECLK;
|
|
input DQSR90;
|
|
input D;
|
|
input RST;
|
|
input RDPNTR2;
|
|
input RDPNTR1;
|
|
input RDPNTR0;
|
|
input WRPNTR2;
|
|
input WRPNTR1;
|
|
input WRPNTR0;
|
|
output Q3;
|
|
output Q2;
|
|
output Q1;
|
|
output Q0;
|
|
output QWL;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module ODDRX1F(SCLK, RST, D0, D1, Q);
|
|
parameter GSR = "ENABLED";
|
|
input SCLK;
|
|
input RST;
|
|
input D0;
|
|
input D1;
|
|
output Q;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module ODDRX2F(SCLK, ECLK, RST, D3, D2, D1, D0, Q);
|
|
parameter GSR = "ENABLED";
|
|
input SCLK;
|
|
input ECLK;
|
|
input RST;
|
|
input D3;
|
|
input D2;
|
|
input D1;
|
|
input D0;
|
|
output Q;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module ODDR71B(SCLK, ECLK, RST, D6, D5, D4, D3, D2, D1, D0, Q);
|
|
parameter GSR = "ENABLED";
|
|
input SCLK;
|
|
input ECLK;
|
|
input RST;
|
|
input D6;
|
|
input D5;
|
|
input D4;
|
|
input D3;
|
|
input D2;
|
|
input D1;
|
|
input D0;
|
|
output Q;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module OSHX2A(D1, D0, SCLK, ECLK, RST, Q);
|
|
parameter GSR = "ENABLED";
|
|
input D1;
|
|
input D0;
|
|
input SCLK;
|
|
input ECLK;
|
|
input RST;
|
|
output Q;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module TSHX2DQA(T1, T0, SCLK, ECLK, DQSW270, RST, Q);
|
|
parameter GSR = "ENABLED";
|
|
parameter REGSET = "SET";
|
|
input T1;
|
|
input T0;
|
|
input SCLK;
|
|
input ECLK;
|
|
input DQSW270;
|
|
input RST;
|
|
output Q;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module TSHX2DQSA(T1, T0, SCLK, ECLK, DQSW, RST, Q);
|
|
parameter GSR = "ENABLED";
|
|
parameter REGSET = "SET";
|
|
input T1;
|
|
input T0;
|
|
input SCLK;
|
|
input ECLK;
|
|
input DQSW;
|
|
input RST;
|
|
output Q;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module ODDRX2DQA(D3, D2, D1, D0, DQSW270, SCLK, ECLK, RST, Q);
|
|
parameter GSR = "ENABLED";
|
|
input D3;
|
|
input D2;
|
|
input D1;
|
|
input D0;
|
|
input DQSW270;
|
|
input SCLK;
|
|
input ECLK;
|
|
input RST;
|
|
output Q;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module ODDRX2DQSB(D3, D2, D1, D0, SCLK, ECLK, DQSW, RST, Q);
|
|
parameter GSR = "ENABLED";
|
|
input D3;
|
|
input D2;
|
|
input D1;
|
|
input D0;
|
|
input SCLK;
|
|
input ECLK;
|
|
input DQSW;
|
|
input RST;
|
|
output Q;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module EHXPLLL(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, STDBY, PLLWAKESYNC, RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK
|
|
, CLKINTFB);
|
|
parameter CLKI_DIV = 1;
|
|
parameter CLKFB_DIV = 1;
|
|
parameter CLKOP_DIV = 8;
|
|
parameter CLKOS_DIV = 8;
|
|
parameter CLKOS2_DIV = 8;
|
|
parameter CLKOS3_DIV = 8;
|
|
parameter CLKOP_ENABLE = "ENABLED";
|
|
parameter CLKOS_ENABLE = "DISABLED";
|
|
parameter CLKOS2_ENABLE = "DISABLED";
|
|
parameter CLKOS3_ENABLE = "DISABLED";
|
|
parameter CLKOP_CPHASE = 0;
|
|
parameter CLKOS_CPHASE = 0;
|
|
parameter CLKOS2_CPHASE = 0;
|
|
parameter CLKOS3_CPHASE = 0;
|
|
parameter CLKOP_FPHASE = 0;
|
|
parameter CLKOS_FPHASE = 0;
|
|
parameter CLKOS2_FPHASE = 0;
|
|
parameter CLKOS3_FPHASE = 0;
|
|
parameter FEEDBK_PATH = "CLKOP";
|
|
parameter CLKOP_TRIM_POL = "RISING";
|
|
parameter CLKOP_TRIM_DELAY = 0;
|
|
parameter CLKOS_TRIM_POL = "RISING";
|
|
parameter CLKOS_TRIM_DELAY = 0;
|
|
parameter OUTDIVIDER_MUXA = "DIVA";
|
|
parameter OUTDIVIDER_MUXB = "DIVB";
|
|
parameter OUTDIVIDER_MUXC = "DIVC";
|
|
parameter OUTDIVIDER_MUXD = "DIVD";
|
|
parameter PLL_LOCK_MODE = 0;
|
|
parameter PLL_LOCK_DELAY = 200;
|
|
parameter STDBY_ENABLE = "DISABLED";
|
|
parameter REFIN_RESET = "DISABLED";
|
|
parameter SYNC_ENABLE = "DISABLED";
|
|
parameter INT_LOCK_STICKY = "ENABLED";
|
|
parameter DPHASE_SOURCE = "DISABLED";
|
|
parameter PLLRST_ENA = "DISABLED";
|
|
parameter INTFB_WAKE = "DISABLED";
|
|
input CLKI;
|
|
input CLKFB;
|
|
input PHASESEL1;
|
|
input PHASESEL0;
|
|
input PHASEDIR;
|
|
input PHASESTEP;
|
|
input PHASELOADREG;
|
|
input STDBY;
|
|
input PLLWAKESYNC;
|
|
input RST;
|
|
input ENCLKOP;
|
|
input ENCLKOS;
|
|
input ENCLKOS2;
|
|
input ENCLKOS3;
|
|
output CLKOP;
|
|
output CLKOS;
|
|
output CLKOS2;
|
|
output CLKOS3;
|
|
output LOCK;
|
|
output INTLOCK;
|
|
output REFCLK;
|
|
output CLKINTFB;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module DTR(STARTPULSE, DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0);
|
|
parameter DTR_TEMP = 25;
|
|
input STARTPULSE;
|
|
output DTROUT7;
|
|
output DTROUT6;
|
|
output DTROUT5;
|
|
output DTROUT4;
|
|
output DTROUT3;
|
|
output DTROUT2;
|
|
output DTROUT1;
|
|
output DTROUT0;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module OSCG(OSC);
|
|
parameter DIV = 128;
|
|
output OSC;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module EXTREFB(REFCLKP, REFCLKN, REFCLKO);
|
|
parameter REFCK_PWDNB = "DONTCARE";
|
|
parameter REFCK_RTERM = "DONTCARE";
|
|
parameter REFCK_DCBIAS_EN = "DONTCARE";
|
|
(* iopad_external_pin *)
|
|
input REFCLKP;
|
|
(* iopad_external_pin *)
|
|
input REFCLKN;
|
|
output REFCLKO;
|
|
endmodule
|
|
|
|
(* blackbox *) (* keep *)
|
|
module JTAGG(TCK, TMS, TDI, JTDO2, JTDO1, TDO, JTDI, JTCK, JRTI2, JRTI1, JSHIFT, JUPDATE, JRSTN, JCE2, JCE1);
|
|
parameter ER1 = "ENABLED";
|
|
parameter ER2 = "ENABLED";
|
|
(* iopad_external_pin *)
|
|
input TCK;
|
|
(* iopad_external_pin *)
|
|
input TMS;
|
|
(* iopad_external_pin *)
|
|
input TDI;
|
|
input JTDO2;
|
|
input JTDO1;
|
|
(* iopad_external_pin *)
|
|
output TDO;
|
|
output JTDI;
|
|
output JTCK;
|
|
output JRTI2;
|
|
output JRTI1;
|
|
output JSHIFT;
|
|
output JUPDATE;
|
|
output JRSTN;
|
|
output JCE2;
|
|
output JCE1;
|
|
endmodule
|
|
|
|
(* blackbox *) (* keep *)
|
|
module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2
|
|
, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, CH0_FF_TX_D_12, CH1_FF_TX_D_12
|
|
, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23
|
|
, CH1_FF_TX_D_23, CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX
|
|
, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB
|
|
, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, CH0_SCIEN, CH1_SCIEN
|
|
, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7
|
|
, D_SCAN_MODE, D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6, D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND
|
|
, D_TXPLL_LOL_TO_ND, CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3
|
|
, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, CH0_FF_RX_D_14
|
|
, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE
|
|
, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE
|
|
, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, D_COUT0, D_COUT1, D_COUT2
|
|
, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, D_REFCLKI, D_FFS_PLOL);
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parameter D_MACROPDB = "DONTCARE";
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parameter D_IB_PWDNB = "DONTCARE";
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parameter D_XGE_MODE = "DONTCARE";
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parameter D_LOW_MARK = "DONTCARE";
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parameter D_HIGH_MARK = "DONTCARE";
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parameter D_BUS8BIT_SEL = "DONTCARE";
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parameter D_CDR_LOL_SET = "DONTCARE";
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parameter D_BITCLK_LOCAL_EN = "DONTCARE";
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parameter D_BITCLK_ND_EN = "DONTCARE";
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parameter D_BITCLK_FROM_ND_EN = "DONTCARE";
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parameter D_SYNC_LOCAL_EN = "DONTCARE";
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parameter D_SYNC_ND_EN = "DONTCARE";
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|
parameter CH0_UC_MODE = "DONTCARE";
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parameter CH1_UC_MODE = "DONTCARE";
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parameter CH0_PCIE_MODE = "DONTCARE";
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parameter CH1_PCIE_MODE = "DONTCARE";
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parameter CH0_RIO_MODE = "DONTCARE";
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parameter CH1_RIO_MODE = "DONTCARE";
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parameter CH0_WA_MODE = "DONTCARE";
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parameter CH1_WA_MODE = "DONTCARE";
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|
parameter CH0_INVERT_RX = "DONTCARE";
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parameter CH1_INVERT_RX = "DONTCARE";
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|
parameter CH0_INVERT_TX = "DONTCARE";
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parameter CH1_INVERT_TX = "DONTCARE";
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parameter CH0_PRBS_SELECTION = "DONTCARE";
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parameter CH1_PRBS_SELECTION = "DONTCARE";
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parameter CH0_GE_AN_ENABLE = "DONTCARE";
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parameter CH1_GE_AN_ENABLE = "DONTCARE";
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parameter CH0_PRBS_LOCK = "DONTCARE";
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parameter CH1_PRBS_LOCK = "DONTCARE";
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parameter CH0_PRBS_ENABLE = "DONTCARE";
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parameter CH1_PRBS_ENABLE = "DONTCARE";
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parameter CH0_ENABLE_CG_ALIGN = "DONTCARE";
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parameter CH1_ENABLE_CG_ALIGN = "DONTCARE";
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parameter CH0_TX_GEAR_MODE = "DONTCARE";
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parameter CH1_TX_GEAR_MODE = "DONTCARE";
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parameter CH0_RX_GEAR_MODE = "DONTCARE";
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parameter CH1_RX_GEAR_MODE = "DONTCARE";
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parameter CH0_PCS_DET_TIME_SEL = "DONTCARE";
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parameter CH1_PCS_DET_TIME_SEL = "DONTCARE";
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|
parameter CH0_PCIE_EI_EN = "DONTCARE";
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|
parameter CH1_PCIE_EI_EN = "DONTCARE";
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|
parameter CH0_TX_GEAR_BYPASS = "DONTCARE";
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|
parameter CH1_TX_GEAR_BYPASS = "DONTCARE";
|
|
parameter CH0_ENC_BYPASS = "DONTCARE";
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|
parameter CH1_ENC_BYPASS = "DONTCARE";
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|
parameter CH0_SB_BYPASS = "DONTCARE";
|
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parameter CH1_SB_BYPASS = "DONTCARE";
|
|
parameter CH0_RX_SB_BYPASS = "DONTCARE";
|
|
parameter CH1_RX_SB_BYPASS = "DONTCARE";
|
|
parameter CH0_WA_BYPASS = "DONTCARE";
|
|
parameter CH1_WA_BYPASS = "DONTCARE";
|
|
parameter CH0_DEC_BYPASS = "DONTCARE";
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|
parameter CH1_DEC_BYPASS = "DONTCARE";
|
|
parameter CH0_CTC_BYPASS = "DONTCARE";
|
|
parameter CH1_CTC_BYPASS = "DONTCARE";
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|
parameter CH0_RX_GEAR_BYPASS = "DONTCARE";
|
|
parameter CH1_RX_GEAR_BYPASS = "DONTCARE";
|
|
parameter CH0_LSM_DISABLE = "DONTCARE";
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|
parameter CH1_LSM_DISABLE = "DONTCARE";
|
|
parameter CH0_MATCH_2_ENABLE = "DONTCARE";
|
|
parameter CH1_MATCH_2_ENABLE = "DONTCARE";
|
|
parameter CH0_MATCH_4_ENABLE = "DONTCARE";
|
|
parameter CH1_MATCH_4_ENABLE = "DONTCARE";
|
|
parameter CH0_MIN_IPG_CNT = "DONTCARE";
|
|
parameter CH1_MIN_IPG_CNT = "DONTCARE";
|
|
parameter CH0_CC_MATCH_1 = "DONTCARE";
|
|
parameter CH1_CC_MATCH_1 = "DONTCARE";
|
|
parameter CH0_CC_MATCH_2 = "DONTCARE";
|
|
parameter CH1_CC_MATCH_2 = "DONTCARE";
|
|
parameter CH0_CC_MATCH_3 = "DONTCARE";
|
|
parameter CH1_CC_MATCH_3 = "DONTCARE";
|
|
parameter CH0_CC_MATCH_4 = "DONTCARE";
|
|
parameter CH1_CC_MATCH_4 = "DONTCARE";
|
|
parameter CH0_UDF_COMMA_MASK = "DONTCARE";
|
|
parameter CH1_UDF_COMMA_MASK = "DONTCARE";
|
|
parameter CH0_UDF_COMMA_A = "DONTCARE";
|
|
parameter CH1_UDF_COMMA_A = "DONTCARE";
|
|
parameter CH0_UDF_COMMA_B = "DONTCARE";
|
|
parameter CH1_UDF_COMMA_B = "DONTCARE";
|
|
parameter CH0_RX_DCO_CK_DIV = "DONTCARE";
|
|
parameter CH1_RX_DCO_CK_DIV = "DONTCARE";
|
|
parameter CH0_RCV_DCC_EN = "DONTCARE";
|
|
parameter CH1_RCV_DCC_EN = "DONTCARE";
|
|
parameter CH0_REQ_LVL_SET = "DONTCARE";
|
|
parameter CH1_REQ_LVL_SET = "DONTCARE";
|
|
parameter CH0_REQ_EN = "DONTCARE";
|
|
parameter CH1_REQ_EN = "DONTCARE";
|
|
parameter CH0_RTERM_RX = "DONTCARE";
|
|
parameter CH1_RTERM_RX = "DONTCARE";
|
|
parameter CH0_PDEN_SEL = "DONTCARE";
|
|
parameter CH1_PDEN_SEL = "DONTCARE";
|
|
parameter CH0_LDR_RX2CORE_SEL = "DONTCARE";
|
|
parameter CH1_LDR_RX2CORE_SEL = "DONTCARE";
|
|
parameter CH0_LDR_CORE2TX_SEL = "DONTCARE";
|
|
parameter CH1_LDR_CORE2TX_SEL = "DONTCARE";
|
|
parameter CH0_TPWDNB = "DONTCARE";
|
|
parameter CH1_TPWDNB = "DONTCARE";
|
|
parameter CH0_RATE_MODE_TX = "DONTCARE";
|
|
parameter CH1_RATE_MODE_TX = "DONTCARE";
|
|
parameter CH0_RTERM_TX = "DONTCARE";
|
|
parameter CH1_RTERM_TX = "DONTCARE";
|
|
parameter CH0_TX_CM_SEL = "DONTCARE";
|
|
parameter CH1_TX_CM_SEL = "DONTCARE";
|
|
parameter CH0_TDRV_PRE_EN = "DONTCARE";
|
|
parameter CH1_TDRV_PRE_EN = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE0_SEL = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE0_SEL = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE1_SEL = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE1_SEL = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE2_SEL = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE2_SEL = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE3_SEL = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE3_SEL = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE4_SEL = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE4_SEL = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE5_SEL = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE5_SEL = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE0_CUR = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE0_CUR = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE1_CUR = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE1_CUR = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE2_CUR = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE2_CUR = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE3_CUR = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE3_CUR = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE4_CUR = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE4_CUR = "DONTCARE";
|
|
parameter CH0_TDRV_SLICE5_CUR = "DONTCARE";
|
|
parameter CH1_TDRV_SLICE5_CUR = "DONTCARE";
|
|
parameter CH0_TDRV_DAT_SEL = "DONTCARE";
|
|
parameter CH1_TDRV_DAT_SEL = "DONTCARE";
|
|
parameter CH0_TX_DIV11_SEL = "DONTCARE";
|
|
parameter CH1_TX_DIV11_SEL = "DONTCARE";
|
|
parameter CH0_RPWDNB = "DONTCARE";
|
|
parameter CH1_RPWDNB = "DONTCARE";
|
|
parameter CH0_RATE_MODE_RX = "DONTCARE";
|
|
parameter CH1_RATE_MODE_RX = "DONTCARE";
|
|
parameter CH0_RLOS_SEL = "DONTCARE";
|
|
parameter CH1_RLOS_SEL = "DONTCARE";
|
|
parameter CH0_RX_LOS_LVL = "DONTCARE";
|
|
parameter CH1_RX_LOS_LVL = "DONTCARE";
|
|
parameter CH0_RX_LOS_CEQ = "DONTCARE";
|
|
parameter CH1_RX_LOS_CEQ = "DONTCARE";
|
|
parameter CH0_RX_LOS_HYST_EN = "DONTCARE";
|
|
parameter CH1_RX_LOS_HYST_EN = "DONTCARE";
|
|
parameter CH0_RX_LOS_EN = "DONTCARE";
|
|
parameter CH1_RX_LOS_EN = "DONTCARE";
|
|
parameter CH0_RX_DIV11_SEL = "DONTCARE";
|
|
parameter CH1_RX_DIV11_SEL = "DONTCARE";
|
|
parameter CH0_SEL_SD_RX_CLK = "DONTCARE";
|
|
parameter CH1_SEL_SD_RX_CLK = "DONTCARE";
|
|
parameter CH0_FF_RX_H_CLK_EN = "DONTCARE";
|
|
parameter CH1_FF_RX_H_CLK_EN = "DONTCARE";
|
|
parameter CH0_FF_RX_F_CLK_DIS = "DONTCARE";
|
|
parameter CH1_FF_RX_F_CLK_DIS = "DONTCARE";
|
|
parameter CH0_FF_TX_H_CLK_EN = "DONTCARE";
|
|
parameter CH1_FF_TX_H_CLK_EN = "DONTCARE";
|
|
parameter CH0_FF_TX_F_CLK_DIS = "DONTCARE";
|
|
parameter CH1_FF_TX_F_CLK_DIS = "DONTCARE";
|
|
parameter CH0_RX_RATE_SEL = "DONTCARE";
|
|
parameter CH1_RX_RATE_SEL = "DONTCARE";
|
|
parameter CH0_TDRV_POST_EN = "DONTCARE";
|
|
parameter CH1_TDRV_POST_EN = "DONTCARE";
|
|
parameter CH0_TX_POST_SIGN = "DONTCARE";
|
|
parameter CH1_TX_POST_SIGN = "DONTCARE";
|
|
parameter CH0_TX_PRE_SIGN = "DONTCARE";
|
|
parameter CH1_TX_PRE_SIGN = "DONTCARE";
|
|
parameter CH0_RXTERM_CM = "DONTCARE";
|
|
parameter CH1_RXTERM_CM = "DONTCARE";
|
|
parameter CH0_RXIN_CM = "DONTCARE";
|
|
parameter CH1_RXIN_CM = "DONTCARE";
|
|
parameter CH0_LEQ_OFFSET_SEL = "DONTCARE";
|
|
parameter CH1_LEQ_OFFSET_SEL = "DONTCARE";
|
|
parameter CH0_LEQ_OFFSET_TRIM = "DONTCARE";
|
|
parameter CH1_LEQ_OFFSET_TRIM = "DONTCARE";
|
|
parameter D_TX_MAX_RATE = "DONTCARE";
|
|
parameter CH0_CDR_MAX_RATE = "DONTCARE";
|
|
parameter CH1_CDR_MAX_RATE = "DONTCARE";
|
|
parameter CH0_TXAMPLITUDE = "DONTCARE";
|
|
parameter CH1_TXAMPLITUDE = "DONTCARE";
|
|
parameter CH0_TXDEPRE = "DONTCARE";
|
|
parameter CH1_TXDEPRE = "DONTCARE";
|
|
parameter CH0_TXDEPOST = "DONTCARE";
|
|
parameter CH1_TXDEPOST = "DONTCARE";
|
|
parameter CH0_PROTOCOL = "DONTCARE";
|
|
parameter CH1_PROTOCOL = "DONTCARE";
|
|
parameter D_ISETLOS = "DONTCARE";
|
|
parameter D_SETIRPOLY_AUX = "DONTCARE";
|
|
parameter D_SETICONST_AUX = "DONTCARE";
|
|
parameter D_SETIRPOLY_CH = "DONTCARE";
|
|
parameter D_SETICONST_CH = "DONTCARE";
|
|
parameter D_REQ_ISET = "DONTCARE";
|
|
parameter D_PD_ISET = "DONTCARE";
|
|
parameter D_DCO_CALIB_TIME_SEL = "DONTCARE";
|
|
parameter CH0_DCOCTLGI = "DONTCARE";
|
|
parameter CH1_DCOCTLGI = "DONTCARE";
|
|
parameter CH0_DCOATDDLY = "DONTCARE";
|
|
parameter CH1_DCOATDDLY = "DONTCARE";
|
|
parameter CH0_DCOATDCFG = "DONTCARE";
|
|
parameter CH1_DCOATDCFG = "DONTCARE";
|
|
parameter CH0_DCOBYPSATD = "DONTCARE";
|
|
parameter CH1_DCOBYPSATD = "DONTCARE";
|
|
parameter CH0_DCOSCALEI = "DONTCARE";
|
|
parameter CH1_DCOSCALEI = "DONTCARE";
|
|
parameter CH0_DCOITUNE4LSB = "DONTCARE";
|
|
parameter CH1_DCOITUNE4LSB = "DONTCARE";
|
|
parameter CH0_DCOIOSTUNE = "DONTCARE";
|
|
parameter CH1_DCOIOSTUNE = "DONTCARE";
|
|
parameter CH0_DCODISBDAVOID = "DONTCARE";
|
|
parameter CH1_DCODISBDAVOID = "DONTCARE";
|
|
parameter CH0_DCOCALDIV = "DONTCARE";
|
|
parameter CH1_DCOCALDIV = "DONTCARE";
|
|
parameter CH0_DCONUOFLSB = "DONTCARE";
|
|
parameter CH1_DCONUOFLSB = "DONTCARE";
|
|
parameter CH0_DCOIUPDNX2 = "DONTCARE";
|
|
parameter CH1_DCOIUPDNX2 = "DONTCARE";
|
|
parameter CH0_DCOSTEP = "DONTCARE";
|
|
parameter CH1_DCOSTEP = "DONTCARE";
|
|
parameter CH0_DCOSTARTVAL = "DONTCARE";
|
|
parameter CH1_DCOSTARTVAL = "DONTCARE";
|
|
parameter CH0_DCOFLTDAC = "DONTCARE";
|
|
parameter CH1_DCOFLTDAC = "DONTCARE";
|
|
parameter CH0_DCOITUNE = "DONTCARE";
|
|
parameter CH1_DCOITUNE = "DONTCARE";
|
|
parameter CH0_DCOFTNRG = "DONTCARE";
|
|
parameter CH1_DCOFTNRG = "DONTCARE";
|
|
parameter CH0_CDR_CNT4SEL = "DONTCARE";
|
|
parameter CH1_CDR_CNT4SEL = "DONTCARE";
|
|
parameter CH0_CDR_CNT8SEL = "DONTCARE";
|
|
parameter CH1_CDR_CNT8SEL = "DONTCARE";
|
|
parameter CH0_BAND_THRESHOLD = "DONTCARE";
|
|
parameter CH1_BAND_THRESHOLD = "DONTCARE";
|
|
parameter CH0_AUTO_FACQ_EN = "DONTCARE";
|
|
parameter CH1_AUTO_FACQ_EN = "DONTCARE";
|
|
parameter CH0_AUTO_CALIB_EN = "DONTCARE";
|
|
parameter CH1_AUTO_CALIB_EN = "DONTCARE";
|
|
parameter CH0_CALIB_CK_MODE = "DONTCARE";
|
|
parameter CH1_CALIB_CK_MODE = "DONTCARE";
|
|
parameter CH0_REG_BAND_OFFSET = "DONTCARE";
|
|
parameter CH1_REG_BAND_OFFSET = "DONTCARE";
|
|
parameter CH0_REG_BAND_SEL = "DONTCARE";
|
|
parameter CH1_REG_BAND_SEL = "DONTCARE";
|
|
parameter CH0_REG_IDAC_SEL = "DONTCARE";
|
|
parameter CH1_REG_IDAC_SEL = "DONTCARE";
|
|
parameter CH0_REG_IDAC_EN = "DONTCARE";
|
|
parameter CH1_REG_IDAC_EN = "DONTCARE";
|
|
parameter D_TXPLL_PWDNB = "DONTCARE";
|
|
parameter D_SETPLLRC = "DONTCARE";
|
|
parameter D_REFCK_MODE = "DONTCARE";
|
|
parameter D_TX_VCO_CK_DIV = "DONTCARE";
|
|
parameter D_PLL_LOL_SET = "DONTCARE";
|
|
parameter D_RG_EN = "DONTCARE";
|
|
parameter D_RG_SET = "DONTCARE";
|
|
parameter D_CMUSETISCL4VCO = "DONTCARE";
|
|
parameter D_CMUSETI4VCO = "DONTCARE";
|
|
parameter D_CMUSETINITVCT = "DONTCARE";
|
|
parameter D_CMUSETZGM = "DONTCARE";
|
|
parameter D_CMUSETP2AGM = "DONTCARE";
|
|
parameter D_CMUSETP1GM = "DONTCARE";
|
|
parameter D_CMUSETI4CPZ = "DONTCARE";
|
|
parameter D_CMUSETI4CPP = "DONTCARE";
|
|
parameter D_CMUSETICP4Z = "DONTCARE";
|
|
parameter D_CMUSETICP4P = "DONTCARE";
|
|
parameter D_CMUSETBIASI = "DONTCARE";
|
|
(* iopad_external_pin *)
|
|
(* iopad_external_pin *)
|
|
input CH0_HDINP;
|
|
(* iopad_external_pin *)
|
|
input CH1_HDINP;
|
|
(* iopad_external_pin *)
|
|
input CH0_HDINN;
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(* iopad_external_pin *)
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input CH1_HDINN;
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input D_TXBIT_CLKP_FROM_ND;
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input D_TXBIT_CLKN_FROM_ND;
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input D_SYNC_ND;
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input D_TXPLL_LOL_FROM_ND;
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input CH0_RX_REFCLK;
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input CH1_RX_REFCLK;
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input CH0_FF_RXI_CLK;
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input CH1_FF_RXI_CLK;
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input CH0_FF_TXI_CLK;
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input CH1_FF_TXI_CLK;
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input CH0_FF_EBRD_CLK;
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input CH1_FF_EBRD_CLK;
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input CH0_FF_TX_D_0;
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input CH1_FF_TX_D_0;
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input CH0_FF_TX_D_1;
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input CH1_FF_TX_D_1;
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input CH0_FF_TX_D_2;
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input CH1_FF_TX_D_2;
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input CH0_FF_TX_D_3;
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input CH1_FF_TX_D_3;
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input CH0_FF_TX_D_4;
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input CH1_FF_TX_D_4;
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input CH0_FF_TX_D_5;
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input CH1_FF_TX_D_5;
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input CH0_FF_TX_D_6;
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input CH1_FF_TX_D_6;
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input CH0_FF_TX_D_7;
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input CH1_FF_TX_D_7;
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input CH0_FF_TX_D_8;
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input CH1_FF_TX_D_8;
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input CH0_FF_TX_D_9;
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input CH1_FF_TX_D_9;
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input CH0_FF_TX_D_10;
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input CH1_FF_TX_D_10;
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input CH0_FF_TX_D_11;
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input CH1_FF_TX_D_11;
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input CH0_FF_TX_D_12;
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input CH1_FF_TX_D_12;
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input CH0_FF_TX_D_13;
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input CH1_FF_TX_D_13;
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input CH0_FF_TX_D_14;
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input CH1_FF_TX_D_14;
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input CH0_FF_TX_D_15;
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input CH1_FF_TX_D_15;
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input CH0_FF_TX_D_16;
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input CH1_FF_TX_D_16;
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input CH0_FF_TX_D_17;
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input CH1_FF_TX_D_17;
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input CH0_FF_TX_D_18;
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input CH1_FF_TX_D_18;
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input CH0_FF_TX_D_19;
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input CH1_FF_TX_D_19;
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input CH0_FF_TX_D_20;
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input CH1_FF_TX_D_20;
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input CH0_FF_TX_D_21;
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input CH1_FF_TX_D_21;
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input CH0_FF_TX_D_22;
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input CH1_FF_TX_D_22;
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input CH0_FF_TX_D_23;
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input CH1_FF_TX_D_23;
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input CH0_FFC_EI_EN;
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input CH1_FFC_EI_EN;
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input CH0_FFC_PCIE_DET_EN;
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input CH1_FFC_PCIE_DET_EN;
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input CH0_FFC_PCIE_CT;
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input CH1_FFC_PCIE_CT;
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input CH0_FFC_SB_INV_RX;
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input CH1_FFC_SB_INV_RX;
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input CH0_FFC_ENABLE_CGALIGN;
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input CH1_FFC_ENABLE_CGALIGN;
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input CH0_FFC_SIGNAL_DETECT;
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input CH1_FFC_SIGNAL_DETECT;
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input CH0_FFC_FB_LOOPBACK;
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input CH1_FFC_FB_LOOPBACK;
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input CH0_FFC_SB_PFIFO_LP;
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input CH1_FFC_SB_PFIFO_LP;
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input CH0_FFC_PFIFO_CLR;
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|
input CH1_FFC_PFIFO_CLR;
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input CH0_FFC_RATE_MODE_RX;
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input CH1_FFC_RATE_MODE_RX;
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|
input CH0_FFC_RATE_MODE_TX;
|
|
input CH1_FFC_RATE_MODE_TX;
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|
input CH0_FFC_DIV11_MODE_RX;
|
|
input CH1_FFC_DIV11_MODE_RX;
|
|
input CH0_FFC_RX_GEAR_MODE;
|
|
input CH1_FFC_RX_GEAR_MODE;
|
|
input CH0_FFC_TX_GEAR_MODE;
|
|
input CH1_FFC_TX_GEAR_MODE;
|
|
input CH0_FFC_DIV11_MODE_TX;
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|
input CH1_FFC_DIV11_MODE_TX;
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|
input CH0_FFC_LDR_CORE2TX_EN;
|
|
input CH1_FFC_LDR_CORE2TX_EN;
|
|
input CH0_FFC_LANE_TX_RST;
|
|
input CH1_FFC_LANE_TX_RST;
|
|
input CH0_FFC_LANE_RX_RST;
|
|
input CH1_FFC_LANE_RX_RST;
|
|
input CH0_FFC_RRST;
|
|
input CH1_FFC_RRST;
|
|
input CH0_FFC_TXPWDNB;
|
|
input CH1_FFC_TXPWDNB;
|
|
input CH0_FFC_RXPWDNB;
|
|
input CH1_FFC_RXPWDNB;
|
|
input CH0_LDR_CORE2TX;
|
|
input CH1_LDR_CORE2TX;
|
|
input D_SCIWDATA0;
|
|
input D_SCIWDATA1;
|
|
input D_SCIWDATA2;
|
|
input D_SCIWDATA3;
|
|
input D_SCIWDATA4;
|
|
input D_SCIWDATA5;
|
|
input D_SCIWDATA6;
|
|
input D_SCIWDATA7;
|
|
input D_SCIADDR0;
|
|
input D_SCIADDR1;
|
|
input D_SCIADDR2;
|
|
input D_SCIADDR3;
|
|
input D_SCIADDR4;
|
|
input D_SCIADDR5;
|
|
input D_SCIENAUX;
|
|
input D_SCISELAUX;
|
|
input CH0_SCIEN;
|
|
input CH1_SCIEN;
|
|
input CH0_SCISEL;
|
|
input CH1_SCISEL;
|
|
input D_SCIRD;
|
|
input D_SCIWSTN;
|
|
input D_CYAWSTN;
|
|
input D_FFC_SYNC_TOGGLE;
|
|
input D_FFC_DUAL_RST;
|
|
input D_FFC_MACRO_RST;
|
|
input D_FFC_MACROPDB;
|
|
input D_FFC_TRST;
|
|
input CH0_FFC_CDR_EN_BITSLIP;
|
|
input CH1_FFC_CDR_EN_BITSLIP;
|
|
input D_SCAN_ENABLE;
|
|
input D_SCAN_IN_0;
|
|
input D_SCAN_IN_1;
|
|
input D_SCAN_IN_2;
|
|
input D_SCAN_IN_3;
|
|
input D_SCAN_IN_4;
|
|
input D_SCAN_IN_5;
|
|
input D_SCAN_IN_6;
|
|
input D_SCAN_IN_7;
|
|
input D_SCAN_MODE;
|
|
input D_SCAN_RESET;
|
|
input D_CIN0;
|
|
input D_CIN1;
|
|
input D_CIN2;
|
|
input D_CIN3;
|
|
input D_CIN4;
|
|
input D_CIN5;
|
|
input D_CIN6;
|
|
input D_CIN7;
|
|
input D_CIN8;
|
|
input D_CIN9;
|
|
input D_CIN10;
|
|
input D_CIN11;
|
|
output CH0_HDOUTP;
|
|
output CH1_HDOUTP;
|
|
output CH0_HDOUTN;
|
|
output CH1_HDOUTN;
|
|
output D_TXBIT_CLKP_TO_ND;
|
|
output D_TXBIT_CLKN_TO_ND;
|
|
output D_SYNC_PULSE2ND;
|
|
output D_TXPLL_LOL_TO_ND;
|
|
output CH0_FF_RX_F_CLK;
|
|
output CH1_FF_RX_F_CLK;
|
|
output CH0_FF_RX_H_CLK;
|
|
output CH1_FF_RX_H_CLK;
|
|
output CH0_FF_TX_F_CLK;
|
|
output CH1_FF_TX_F_CLK;
|
|
output CH0_FF_TX_H_CLK;
|
|
output CH1_FF_TX_H_CLK;
|
|
output CH0_FF_RX_PCLK;
|
|
output CH1_FF_RX_PCLK;
|
|
output CH0_FF_TX_PCLK;
|
|
output CH1_FF_TX_PCLK;
|
|
output CH0_FF_RX_D_0;
|
|
output CH1_FF_RX_D_0;
|
|
output CH0_FF_RX_D_1;
|
|
output CH1_FF_RX_D_1;
|
|
output CH0_FF_RX_D_2;
|
|
output CH1_FF_RX_D_2;
|
|
output CH0_FF_RX_D_3;
|
|
output CH1_FF_RX_D_3;
|
|
output CH0_FF_RX_D_4;
|
|
output CH1_FF_RX_D_4;
|
|
output CH0_FF_RX_D_5;
|
|
output CH1_FF_RX_D_5;
|
|
output CH0_FF_RX_D_6;
|
|
output CH1_FF_RX_D_6;
|
|
output CH0_FF_RX_D_7;
|
|
output CH1_FF_RX_D_7;
|
|
output CH0_FF_RX_D_8;
|
|
output CH1_FF_RX_D_8;
|
|
output CH0_FF_RX_D_9;
|
|
output CH1_FF_RX_D_9;
|
|
output CH0_FF_RX_D_10;
|
|
output CH1_FF_RX_D_10;
|
|
output CH0_FF_RX_D_11;
|
|
output CH1_FF_RX_D_11;
|
|
output CH0_FF_RX_D_12;
|
|
output CH1_FF_RX_D_12;
|
|
output CH0_FF_RX_D_13;
|
|
output CH1_FF_RX_D_13;
|
|
output CH0_FF_RX_D_14;
|
|
output CH1_FF_RX_D_14;
|
|
output CH0_FF_RX_D_15;
|
|
output CH1_FF_RX_D_15;
|
|
output CH0_FF_RX_D_16;
|
|
output CH1_FF_RX_D_16;
|
|
output CH0_FF_RX_D_17;
|
|
output CH1_FF_RX_D_17;
|
|
output CH0_FF_RX_D_18;
|
|
output CH1_FF_RX_D_18;
|
|
output CH0_FF_RX_D_19;
|
|
output CH1_FF_RX_D_19;
|
|
output CH0_FF_RX_D_20;
|
|
output CH1_FF_RX_D_20;
|
|
output CH0_FF_RX_D_21;
|
|
output CH1_FF_RX_D_21;
|
|
output CH0_FF_RX_D_22;
|
|
output CH1_FF_RX_D_22;
|
|
output CH0_FF_RX_D_23;
|
|
output CH1_FF_RX_D_23;
|
|
output CH0_FFS_PCIE_DONE;
|
|
output CH1_FFS_PCIE_DONE;
|
|
output CH0_FFS_PCIE_CON;
|
|
output CH1_FFS_PCIE_CON;
|
|
output CH0_FFS_RLOS;
|
|
output CH1_FFS_RLOS;
|
|
output CH0_FFS_LS_SYNC_STATUS;
|
|
output CH1_FFS_LS_SYNC_STATUS;
|
|
output CH0_FFS_CC_UNDERRUN;
|
|
output CH1_FFS_CC_UNDERRUN;
|
|
output CH0_FFS_CC_OVERRUN;
|
|
output CH1_FFS_CC_OVERRUN;
|
|
output CH0_FFS_RXFBFIFO_ERROR;
|
|
output CH1_FFS_RXFBFIFO_ERROR;
|
|
output CH0_FFS_TXFBFIFO_ERROR;
|
|
output CH1_FFS_TXFBFIFO_ERROR;
|
|
output CH0_FFS_RLOL;
|
|
output CH1_FFS_RLOL;
|
|
output CH0_FFS_SKP_ADDED;
|
|
output CH1_FFS_SKP_ADDED;
|
|
output CH0_FFS_SKP_DELETED;
|
|
output CH1_FFS_SKP_DELETED;
|
|
output CH0_LDR_RX2CORE;
|
|
output CH1_LDR_RX2CORE;
|
|
output D_SCIRDATA0;
|
|
output D_SCIRDATA1;
|
|
output D_SCIRDATA2;
|
|
output D_SCIRDATA3;
|
|
output D_SCIRDATA4;
|
|
output D_SCIRDATA5;
|
|
output D_SCIRDATA6;
|
|
output D_SCIRDATA7;
|
|
output D_SCIINT;
|
|
output D_SCAN_OUT_0;
|
|
output D_SCAN_OUT_1;
|
|
output D_SCAN_OUT_2;
|
|
output D_SCAN_OUT_3;
|
|
output D_SCAN_OUT_4;
|
|
output D_SCAN_OUT_5;
|
|
output D_SCAN_OUT_6;
|
|
output D_SCAN_OUT_7;
|
|
output D_COUT0;
|
|
output D_COUT1;
|
|
output D_COUT2;
|
|
output D_COUT3;
|
|
output D_COUT4;
|
|
output D_COUT5;
|
|
output D_COUT6;
|
|
output D_COUT7;
|
|
output D_COUT8;
|
|
output D_COUT9;
|
|
output D_COUT10;
|
|
output D_COUT11;
|
|
output D_COUT12;
|
|
output D_COUT13;
|
|
output D_COUT14;
|
|
output D_COUT15;
|
|
output D_COUT16;
|
|
output D_COUT17;
|
|
output D_COUT18;
|
|
output D_COUT19;
|
|
input D_REFCLKI;
|
|
output D_FFS_PLOL;
|
|
endmodule
|
|
|