3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-03-25 13:58:39 +00:00
yosys/techlibs/lattice
2026-01-28 07:45:58 +13:00
..
tests
arith_map_ccu2c.v
arith_map_ccu2d.v
arith_map_nexus.v
brams_8kc.txt
brams_16kd.txt
brams_map_8kc.v
brams_map_16kd.v
brams_map_nexus.v
brams_nexus.txt
ccu2c_sim.vh
ccu2d_sim.vh
cells_bb_ecp5.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
cells_bb_nexus.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
cells_bb_xo2.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
cells_bb_xo3.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
cells_bb_xo3d.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
cells_ff.vh
cells_io.vh
cells_map_nexus.v
cells_map_trellis.v
cells_sim_ecp5.v
cells_sim_nexus.v
cells_sim_xo2.v
cells_sim_xo3.v
cells_sim_xo3d.v
cells_xtra.py
cells_xtra_nexus.py
common_sim.vh
dsp_map_18x18.v
dsp_map_nexus.v
latches_map.v
lattice_gsr.cc
lrams_map_nexus.v
lrams_nexus.txt
lutrams_map_nexus.v
lutrams_map_trellis.v
lutrams_nexus.txt
lutrams_trellis.txt
Makefile.inc
parse_init.vh
synth_lattice.cc