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yosys/techlibs
History
Emil J. Tywoniak dcc74755e7 WIP
2026-06-15 11:26:09 +02:00
..
achronix Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00
analogdevices Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00
anlogic WIP 2026-06-12 00:18:53 +02:00
common WIP 2026-06-12 00:18:53 +02:00
coolrunner2 WIP 2026-06-15 11:26:09 +02:00
easic Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00
efinix WIP 2026-06-12 00:18:53 +02:00
fabulous Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00
gatemate WIP 2026-06-12 00:18:53 +02:00
gowin gowin: replace positional arguments in cells_sim.v with named 2026-05-22 18:39:42 +02:00
greenpak4 WIP 2026-06-12 00:18:53 +02:00
ice40 WIP 2026-06-12 16:25:07 +02:00
intel Revert "intel: register bram celltypes" 2026-05-22 18:40:16 +02:00
intel_alm Revert "intel: register bram celltypes" 2026-05-22 18:40:16 +02:00
lattice WIP 2026-06-12 00:18:53 +02:00
microchip WIP 2026-06-12 16:25:07 +02:00
nanoxplore WIP 2026-06-11 13:17:54 +02:00
quicklogic WIP 2026-06-12 16:25:07 +02:00
sf2 Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00
xilinx WIP 2026-06-12 16:25:07 +02:00
.gitignore pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
fix_mod.py Add and use fix_mod.py 2026-01-28 07:45:58 +13:00