3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-14 09:55:37 +00:00
yosys/techlibs/quicklogic/qlf_k6n10f
2026-06-23 07:24:59 +02:00
..
.gitignore quicklogic: Generate bram_types_sim.v at build time 2023-12-04 18:21:00 +01:00
arith_map.v End of file fix 2026-06-23 07:23:41 +02:00
brams_map.v End of file fix 2026-06-23 07:23:41 +02:00
brams_sim.v End of file fix 2026-06-23 07:23:41 +02:00
cells_sim.v End of file fix 2026-06-23 07:23:41 +02:00
dsp_final_map.v End of file fix 2026-06-23 07:23:41 +02:00
dsp_map.v
dsp_sim.v
ffs_map.v End of file fix 2026-06-23 07:23:41 +02:00
generate_bram_types_sim.py Drop timestamp in generate_bram_types_sim.py 2024-10-30 08:47:18 +01:00
libmap_brams.txt
libmap_brams_map.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
sram1024x18_mem.v End of file fix 2026-06-23 07:23:41 +02:00
TDP18K_FIFO.v
ufifo_ctl.v