techlibs: fix typo in help message 
						
					 
				 
				2023-11-13 16:29:52 +13:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Fix some synth_* help messages 
						
					 
				 
				2024-03-18 11:33:18 +13:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Make all vector-size related integer params in $print sim model signed 
						
					 
				 
				2025-03-25 13:08:49 +00:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Blackbox all whiteboxes after synthesis 
						
					 
				 
				2021-03-17 21:07:20 +00:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Fixing old e-mail addresses and deadnames 
						
					 
				 
				2021-06-08 00:39:36 +02:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Changing non clocked alway assignment to blocking. 
						
					 
				 
				2025-04-23 16:59:53 +02:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Merge pull request  #4285  from YosysHQ/typo_fixup 
						
					 
				 
				2024-04-25 09:54:48 +12:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Fix some synth_* help messages 
						
					 
				 
				2024-03-18 11:33:18 +13:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							gatemate: Set unused BRAM inputs to 'bx 
						
					 
				 
				2025-04-28 14:42:16 +02:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Gowin. BUGFIX. Fix multi-line descriptions. 
						
					 
				 
				2025-07-02 12:39:18 +10:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Change to use blocking assignments in non-clocked processes. 
						
					 
				 
				2025-04-23 17:21:32 +02:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							ice40_dsp: add unextend_unsigned function 
						
					 
				 
				2025-04-11 19:41:35 +03:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Removed SystemVerilog module end label 
						
					 
				 
				2024-03-19 01:31:36 +01:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							intel_alm: drop quartus support 
						
					 
				 
				2024-05-03 11:32:33 +01:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Fix some synth_* help messages 
						
					 
				 
				2024-03-18 11:33:18 +13:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							pmgen: Move passes out of pmgen folder 
						
					 
				 
				2025-01-31 15:18:28 +13:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Cleanup of synth_nanoxplore pass 
						
					 
				 
				2024-09-03 10:15:50 +02:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Fix some synth_* help messages 
						
					 
				 
				2024-03-18 11:33:18 +13:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							create duplicate IOFFs if multiple output ports are connected to the same register 
						
					 
				 
				2025-01-31 11:28:57 +01:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							Test fixes for latest iverilog 
						
					 
				 
				2022-09-21 15:46:43 +02:00  
		
			
			
			
			
				
					
						
							
								
								
									
									
									 
							
						
					 
				 
				
					
						
							
							URAM mapping : Add test for 2048 x 144b 
						
					 
				 
				2025-05-10 14:53:56 +02:00  
		
			
			
			
			
				
					
						
							
								 
				 
				
					
						
							
							pmgen: Move passes out of pmgen folder 
						
					 
				 
				2025-01-31 15:18:28 +13:00