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yosys/tests/arch/intel_le/blockram.ys
2020-11-03 00:35:35 +01:00

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read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 9 sync_ram_sdp
synth_intel_le -family cycloneiv
cd sync_ram_sdp
select -assert-count 1 t:MISTRAL_M9K
select -assert-none t:MISTRAL_M9K %% t:* %D