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126 lines
2.4 KiB
Verilog
126 lines
2.4 KiB
Verilog
// The core logic primitive of the Cyclone IVE/IVGX is the Logic Element
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// (LE). Each LE is made up of an 4-input, 1-output look-up table, covered
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// in this file, connected to combinational outputs, a carry chain, and one
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// D flip-flop (which are covered as MISTRAL_FF in dff_sim.v).
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//
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// LEs are have two modes of operation
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//
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// Normal (combinational) mode
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// ---------------------------
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// The LE can implement:
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// - a single 4-input(or less) function
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//
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// Normal-mode functions are represented as MISTRAL_ALUTN cells with N inputs.
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//
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// Arithmetic mode
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// ---------------
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// In arithmetic mode, LE implements two bit adder and carry chain
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// It can drive either registered or unregistered output.
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//
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// The cell for an arithmetic-mode is MISTRAL_ALM_ARITH.
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//
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`default_nettype none
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// Cyclone V LUT output timings (picoseconds):
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//
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// CARRY A B C D
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// COMBOUT ?408? 319 323 211 114
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// CARRYOUT 200 376 385 ? -
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT4(input A, B, C, D, output Q);
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parameter [15:0] LUT = 16'h0000;
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`ifdef cycloneiv
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specify
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(A => Q) = 319;
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(B => Q) = 323;
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(C => Q) = 211;
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(D => Q) = 114;
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endspecify
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`endif
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assign Q = LUT >> {D, C, B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT3(input A, B, C, output Q);
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parameter [7:0] LUT = 8'h00;
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`ifdef cycloneiv
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specify
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(A => Q) = 510;
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(B => Q) = 400;
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(C => Q) = 97;
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endspecify
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`endif
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assign Q = LUT >> {C, B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT2(input A, B, output Q);
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parameter [3:0] LUT = 4'h0;
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`ifdef cycloneiv
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specify
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(A => Q) = 400;
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(B => Q) = 97;
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endspecify
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`endif
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assign Q = LUT >> {B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_NOT(input A, output Q);
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`ifdef cycloneiv
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specify
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(A => Q) = 97;
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endspecify
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`endif
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assign Q = ~A;
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endmodule
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(* abc9_box, lib_whitebox *)
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module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);
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parameter LUT = 16'h0000;
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`ifdef cycloneiv
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specify
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(A => SO) = 1342;
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(B => SO) = 1323;
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(C => SO) = 927;
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(D => SO) = 887;
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(CI => SO) = 368;
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(A => CO) = 376;
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(B => CO) = 385;
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(CI => CO) = 200;
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endspecify
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`endif
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wire q0, q1;
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assign q0 = LUT >> {'b0, CI, B, A};
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assign q1 = LUT >> {D, CI, B, A};
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assign SO = q1;
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assign CO = q0;
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endmodule
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