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yosys/frontends
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Zachary Snow 8de2e863af verilog: support recursive functions using ternary expressions 
This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.
2021-02-12 14:43:42 -05:00
..
aiger Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
ast verilog: support recursive functions using ternary expressions 2021-02-12 14:43:42 -05:00
blif Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
json Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
liberty Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
rpc Fix argument handling in connect_rpc 2020-10-19 13:40:57 +02:00
rtlil rtlil: remove dotted identifiers. 2020-11-25 16:47:20 +00:00
verific Ganulate Verific support 2021-02-12 10:08:43 +01:00
verilog Merge pull request #2578 from zachjs/genblk-port 2021-02-11 10:26:49 -05:00