mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-23 21:09:14 +00:00
6 lines
107 B
Verilog
6 lines
107 B
Verilog
module add_wide_output(
|
|
input [7:0] a, b, c, d,
|
|
output [31:0] y
|
|
);
|
|
assign y = a + b + c + d;
|
|
endmodule
|