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yosys/frontends/verilog
2020-06-18 23:34:52 +00:00
..
.gitignore
const2ast.cc Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
Makefile.inc
preproc.cc MSVC does not understand __builtin_unreachable 2020-06-17 15:10:08 +02:00
preproc.h Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
verilog_frontend.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
verilog_frontend.h frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
verilog_lexer.l Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
verilog_parser.y MSVC cannot omit operand in conditional 2020-06-17 15:10:08 +02:00