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73 lines
2.3 KiB
Text
73 lines
2.3 KiB
Text
### TODO: Not running equivalence checking because BRAM models does not exists
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### currently. Checking instance counts instead.
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# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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# Anything memory bits < 1024 -> LUTRAM
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 0 t:RAMB18E1
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select -assert-count 4 t:RAM64M
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# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB36E1
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### With parameters
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design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
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setattr -setstr ram_style block m:memory
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
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setattr -set logic_block 1 m:memory
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 0 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
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setattr -setstr ram_style block m:memory
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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