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https://github.com/YosysHQ/yosys
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Tests: Use setattr -setstr
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parent
4006dafefc
commit
7630e24bbf
5 changed files with 25 additions and 25 deletions
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@ -19,14 +19,14 @@ select -assert-count 9 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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setattr -setstr syn_ramstyle block_ram m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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setattr -setstr syn_ramstyle Block_RAM m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD # any case works
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@ -41,7 +41,7 @@ select -assert-count 9 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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setattr -setstr syn_ramstyle registers m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 180 t:TRELLIS_FF
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@ -98,14 +98,14 @@ select -assert-count 5 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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setattr -setstr syn_ramstyle block_ram m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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setattr -setstr syn_ramstyle Block_RAM m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD # any case works
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@ -120,7 +120,7 @@ select -assert-count 5 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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setattr -setstr syn_ramstyle registers m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 90 t:TRELLIS_FF
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@ -146,14 +146,14 @@ select -assert-count 1 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "distributed" m:memory
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setattr -setstr syn_ramstyle distributed m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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setattr -setstr syn_ramstyle registers m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
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select -assert-count 68 t:TRELLIS_FF
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@ -187,7 +187,7 @@ select -assert-min 18 t:LUT4
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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setattr -setstr syn_romstyle ebr m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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@ -201,7 +201,7 @@ select -assert-count 1 t:DP16KD
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "logic" m:memory
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setattr -setstr syn_romstyle logic m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # requested LUTROM explicitly
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select -assert-min 18 t:LUT4
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@ -234,7 +234,7 @@ select -assert-min 9 t:LUT4
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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setattr -setstr syn_romstyle ebr m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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@ -248,7 +248,7 @@ select -assert-count 1 t:DP16KD
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "logic" m:memory
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setattr -setstr syn_romstyle logic m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # requested LUTROM explicitly
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select -assert-min 9 t:LUT4
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@ -37,14 +37,14 @@ select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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setattr -setstr syn_ramstyle block_ram m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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setattr -setstr syn_ramstyle Block_RAM m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K # any case works
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@ -58,7 +58,7 @@ select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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setattr -setstr syn_ramstyle registers m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
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select -assert-min 1 t:SB_DFFE
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@ -110,7 +110,7 @@ select -assert-min 1 t:SB_LUT4
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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setattr -setstr syn_romstyle ebr m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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@ -124,7 +124,7 @@ select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "logic" m:memory
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setattr -setstr syn_romstyle logic m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
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select -assert-min 1 t:SB_LUT4
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@ -16,7 +16,7 @@ select -assert-count 1 t:RAM32M
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# Set ram_style distributed to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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setattr -set ram_style "distributed" block_ram/m:*
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setattr -setstr ram_style distributed block_ram/m:*
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synth_xilinx -top block_ram -noiopad
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 16 t:RAM256X1S
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@ -51,7 +51,7 @@ select -assert-count 1 t:RAMB36E1
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design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
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setattr -set ram_style "block" m:memory
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setattr -setstr ram_style block m:memory
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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@ -67,7 +67,7 @@ select -assert-count 0 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
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setattr -set ram_style "block" m:memory
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setattr -setstr ram_style block m:memory
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synth_xilinx -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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@ -82,7 +82,7 @@ select -assert-count 0 w:clk2 %a %co t:clkbuf %i
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design -load ref
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setattr -set clkbuf_inhibit 1 w:clk1
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setattr -set buffer_type "bufg" w:clk2
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setattr -setstr buffer_type bufg w:clk2
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clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
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select -assert-count 3 top/t:clkbuf
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select -assert-count 3 sub/t:clkbuf
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@ -98,10 +98,10 @@ select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0
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# ----------------------
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design -load ref
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setattr -set buffer_type "none" w:clk1
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setattr -set buffer_type "bufr" w:clk2
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setattr -set buffer_type "bufr" w:sclk4
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setattr -set buffer_type "bufr" w:sclk5
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setattr -setstr buffer_type none w:clk1
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setattr -setstr buffer_type bufr w:clk2
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setattr -setstr buffer_type bufr w:sclk4
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setattr -setstr buffer_type bufr w:sclk5
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clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
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select -assert-count 0 w:clk1 %a %co t:clkbuf %i
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select -assert-count 0 w:clk2 %a %co t:clkbuf %i
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