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yosys/techlibs/machxo2
2021-02-23 17:39:58 +01:00
..
cells_map.v machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. 2021-02-23 17:39:58 +01:00
cells_sim.v machxo2: Fix typos in FACADE_FF sim model. 2021-02-23 17:39:58 +01:00
Makefile.inc machxo2: Create basic techlibs and synth_machxo2 pass. 2021-02-23 17:39:58 +01:00
synth_machxo2.cc machxo2: Improve help_mode output in synth_machxo2. 2021-02-23 17:39:58 +01:00