Akash Levy 210ec6585f Merge branch 'YosysHQ:main' into main		2024-09-16 06:59:25 -07:00
..
aiger	read_aiger: Fix incorrect read of binary Aiger without outputs	2024-04-29 14:06:58 +01:00
arch	add min_ce_use and min_srst_use parameters	2024-08-15 17:50:36 +02:00
asicworld
bind
blif
bram
cxxrtl	cxxxrtl: fix use of format specifiers in test	2024-06-11 07:22:39 +01:00
errors
fmt
fsm
functional	functional tests: run from make tests but not smtlib/rkt tests	2024-09-04 10:30:08 +01:00
hana
liberty	Extend liberty tests	2024-08-13 18:47:36 +02:00
lut
memfile
memlib	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
memories	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
opt	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
opt_share
proc	proc_dff: add tests	2024-08-28 16:24:47 +01:00
realmath
rpc
sat	Add support for $dimensions and $unpacked_dimensions	2024-02-11 11:26:52 -05:00
select
share
sim
simple	write_verilog: don't assign to a reg.	2024-04-03 13:06:45 +02:00
simple_abc9
smv
sva	tests/sva: Skip sva tests that use SBY until SBY is compatible again	2024-03-05 14:37:33 +01:00
svinterfaces
svtypes	Modifications	2024-03-21 11:31:43 -07:00
techmap	clockgate: EN can be a bit on a multi-bit wire	2024-09-11 19:18:25 +02:00
tools
unit	Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc	2024-02-25 17:23:56 +01:00
various	Merge branch 'YosysHQ:main' into master	2024-08-21 18:52:38 -07:00
verific	Merge branch 'YosysHQ:main' into main	2024-09-12 11:14:15 -07:00
verilog	write_verilog: don't assign to a reg.	2024-04-03 13:06:45 +02:00
vloghtb
xprop	tests: Comment on A[0]	2024-02-16 11:43:28 +01:00
gen-tests-makefile.sh	do not override existing shell variable	2024-02-12 12:58:13 +01:00