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yosys/tests/verific
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Akash Levy 3e9a5c68b1 Switch back to main Verific without VHDL support
2026-02-18 21:57:14 -08:00
..
blackbox.ys.DISABLED
blackbox_empty.ys.DISABLED
blackbox_ql.ys.DISABLED
bounds.sv
bounds.vhd
case.sv
case.ys
chformal.ys.DISABLED
clocking.ys
enum_values.sv
enum_values.ys
ext_ramnet_err.sv
ext_ramnet_err.ys
import_warning_operator.vhd
memory_semantics.ys.DISABLED
mixed_flist.flist
mixed_flist.sv
mixed_flist.vhd
mixed_flist.ys.DISABLED Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
port_bus_order.ys
range_case.sv
range_case.ys
README.md Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
rom_case.ys.DISABLED
run-test.sh
setenv.flist
setenv.ys
sva_continue_on_err.ys
sva_continue_on_err_explosion.ys
sva_no_continue_on_err.ys

README.md

Verific Test Cases

Disabled

  • import_warning_operator: no VHDL
  • mixed_flist: no VHDL
  • memory_semantics: relies on initial values being retained, which we do not want
  • rom_case: we need different behavior for multi-port memories
  • blackbox*: we need different behavior for parametrized blackboxes
  • chformal: relies on initial values being retained, which we do not want