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https://github.com/YosysHQ/yosys
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113 lines
2.8 KiB
Text
113 lines
2.8 KiB
Text
read_verilog -specify << EOT
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module top(input a, b, output o);
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wire c, d, e;
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bb #(.SOME_PARAM(1)) bb1 (.a (a), .b (b), .o (c));
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bb #(.SOME_PARAM(2)) bb2 (.a (a), .b (b), .o (d));
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wb wb1 (.a (a), .b (b), .o (e));
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some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
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endmodule
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(* blackbox *)
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module bb #( parameter SOME_PARAM=0 ) (input a, b, output o);
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assign o = a | b;
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specify
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(a => o) = 1;
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endspecify
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endmodule
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(* whitebox *)
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module wb(input a, b, output o);
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assign o = a ^ b;
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endmodule
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module some_mod(input a, b, c, output o);
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assign o = a & (b | c);
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endmodule
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EOT
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hierarchy -top top
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design -save hier
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select -assert-none t:$anyseq
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select -assert-count 3 =t:?b
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cutpoint -blackbox
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select -assert-none =t:?b
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select -assert-none r:SOME_PARAM
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select -assert-count 3 t:$anyseq
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select -assert-count 3 t:$scopeinfo
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select -assert-count 3 t:$scopeinfo r:TYPE=blackbox %i
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select -assert-count 3 t:$scopeinfo n:*cutpoint.cc* %i
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# -noscopeinfo works with -blackbox
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design -load hier
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cutpoint -blackbox -noscopeinfo
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select -assert-none t:$scopeinfo
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# cutpoint -blackbox === cutpoint =A:whitebox =A:blackbox %u %C
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# (simplified to =A:*box %C)
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design -load hier
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cutpoint -blackbox
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rename -enumerate -pattern A_% t:$scopeinfo
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rename -enumerate -pattern B_% t:$anyseq
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rename -enumerate -pattern C_% w:*Anyseq*
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design -save gold
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select -write cutpoint.gold.sel =*
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design -load hier
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cutpoint =A:*box %C
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rename -enumerate -pattern A_% t:$scopeinfo
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rename -enumerate -pattern B_% t:$anyseq
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rename -enumerate -pattern C_% w:*Anyseq*
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design -save gate
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select -write cutpoint.gate.sel
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select -read cutpoint.gold.sel
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# nothing in gate but not gold
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select -assert-none % %n
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design -load gold
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select -read cutpoint.gate.sel
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# nothing in gold but not gate
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select -assert-none % %n
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# replacing the blackbox with a verific-style unknown module should work too
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# (note this specific example loses the values of SOME_PARAM which would
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# normally be retained by verific)
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design -load hier
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delete =bb
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read_rtlil << EOT
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attribute \blackbox 1
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module \bb
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parameter \SOME_PARAM 0
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wire inout 3 \o
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wire inout 2 \b
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wire inout 1 \a
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end
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EOT
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cutpoint -blackbox
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check -assert
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# also concatenated signals, and signals between two inout ports
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design -load hier
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delete top =bb
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read_verilog << EOT
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module top(input [1:0] a, b, output [1:0] o);
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wire [1:0] c, d, e;
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bb #(.SOME_PARAM(1)) bb1 (.a ({a[0], e[1]}), .b (b), .o (c));
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bb #(.SOME_PARAM(2)) bb2 (.a ({c[1], a[0]}), .b (c), .o (d));
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wb wb1 (.a (a), .b (b), .o (e));
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some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
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endmodule
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EOT
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read_rtlil << EOT
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attribute \blackbox 1
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module \bb
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parameter \SOME_PARAM 0
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wire inout 3 width 2 \o
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wire inout 2 width 2 \b
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wire inout 1 width 2 \a
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end
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EOT
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cutpoint -blackbox
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check -assert
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