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yosys/techlibs/xilinx
History
Eddie Hung 601fac97e4 Add params
2019-07-18 21:02:49 -07:00
..
tests
.gitignore
abc_xc7.box Fix $__XILINX_MUXF78 box timing 2019-07-01 14:04:06 -07:00
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
cells_map.v xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) 2019-07-16 16:47:53 +01:00
cells_sim.v Signedness 2019-07-16 15:54:27 -07:00
cells_xtra.sh
cells_xtra.v Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim 2019-07-15 11:13:22 -07:00
drams.txt
drams_map.v
dsp_map.v Add params 2019-07-18 21:02:49 -07:00
ff_map.v xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado. 2019-07-11 21:13:12 +02:00
lut_map.v
Makefile.inc Oops forgot these files 2019-07-15 15:03:15 -07:00
mux_map.v
synth_xilinx.cc Use single DSP_SIGNEDONLY macro 2019-07-18 13:09:55 -07:00
xc6s_brams.txt synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc6s_brams_bb.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc6s_brams_map.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc7_brams.txt synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc7_brams_bb.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc7_brams_map.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00