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yosys/tests/verific
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Akash Levy 1dcf75d175 Sync
2024-12-19 21:40:30 -08:00
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.gitignore Add test example 2023-02-27 09:24:04 +01:00
blackbox.ys verific->import fix for new test case 2024-12-02 20:07:07 -05:00
blackbox_empty.ys Add verific verilog test cases for blackboxes 2024-12-06 16:13:25 +01:00
blackbox_ql.ys Add verific verilog test cases for blackboxes 2024-12-06 16:13:25 +01:00
bounds.sv bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
bounds.vhd bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
bounds.ys.DISABLED Merge remote-tracking branch 'upstream/main' 2024-12-12 22:49:19 -08:00
case.sv Add test example 2023-02-27 09:24:04 +01:00
case.ys Fixups 2024-09-23 04:25:10 -07:00
clocking.ys Clocking works with -formal flag 2024-09-22 08:01:16 -07:00
enum_values.sv verific: Fix enum_values support and signed attribute values 2023-03-15 09:51:36 +01:00
enum_values.ys verific: Fix enum_values support and signed attribute values 2023-03-15 09:51:36 +01:00
memory_semantics.ys.DISABLED Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
range_case.sv Added ranged case check 2023-02-27 09:24:04 +01:00
range_case.ys Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
README.md Update Verific 2024-10-02 23:09:36 -07:00
rom_case.ys.DISABLED Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
run-test.sh test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
setenv.flist add setenv pass 2024-12-06 11:25:43 +01:00
setenv.ys add setenv pass 2024-12-06 11:25:43 +01:00

README.md

Verific Test Cases

Disabled

  • bounds: checks top and bottom bound attributes, which are removed to avoid OpenSTA issues
  • memory_semantics: relies on initial values being retained, which we do not want
  • rom_case: relies on using Verific's VHDL frontend rather than GHDL