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.gitignore
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quicklogic: Generate bram_types_sim.v at build time
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2023-12-04 18:21:00 +01:00 |
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arith_map.v
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change ql-bram-types pass to use mode parameter; clean up primitive libraries
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2023-12-04 15:52:02 +01:00 |
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brams_map.v
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merge brams_final_map.v into brams_map.v
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2023-12-04 15:52:02 +01:00 |
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brams_sim.v
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quicklogic: Add missing RAM_INIT param on TDP36K sim model
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2023-12-04 15:52:03 +01:00 |
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cells_sim.v
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quicklogic: Drop blackbox off adder_carry
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2023-12-04 15:52:03 +01:00 |
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dspv1_final_map.v
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quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
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2025-03-11 10:35:31 +01:00 |
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dspv1_map.v
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synth_quicklogic: add -dspv2 to opt into v2 DSP blocks
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2025-03-11 10:35:30 +01:00 |
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dspv1_sim.v
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quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
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2025-03-11 10:35:31 +01:00 |
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dspv1_sim_extra.v
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quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
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2025-03-11 10:35:31 +01:00 |
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dspv2_map.v
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quicklogic: update dspv2_sim.v to v1.1 Feb21
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2025-03-11 10:35:31 +01:00 |
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dspv2_sim.v
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quicklogic: update dspv2_sim.v to v1.1 Feb21
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2025-03-11 10:35:31 +01:00 |
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ffs_map.v
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change ql-bram-types pass to use mode parameter; clean up primitive libraries
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2023-12-04 15:52:02 +01:00 |
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generate_bram_types_sim.py
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Drop timestamp in generate_bram_types_sim.py
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2024-10-30 08:47:18 +01:00 |
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libmap_brams.txt
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add qlf_k6n10f architecture + bram inference
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2023-12-04 15:52:02 +01:00 |
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libmap_brams_map.v
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quicklogic: Test TDP36K inference with initial data
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2023-12-04 15:52:03 +01:00 |
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sram1024x18_mem.v
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add example memory test
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2023-12-04 15:52:03 +01:00 |
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TDP18K_FIFO.v
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add example memory test
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2023-12-04 15:52:03 +01:00 |
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ufifo_ctl.v
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add example memory test
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2023-12-04 15:52:03 +01:00 |
