| .. | 
		
		
			
			
			
			
				| .gitignore | Speed up "make test" and related cleanups | 2019-08-17 14:37:07 +02:00 | 
		
			
			
			
			
				| abc9.v | Another sloppy mistake! | 2019-11-21 16:33:20 -08:00 | 
		
			
			
			
			
				| abc9.ys | write_xaiger: fix for (* keep *) on flop output | 2020-01-21 09:43:04 -08:00 | 
		
			
			
			
			
				| async.sh | Improve tests/various/async, disable failing ffl test | 2019-07-09 22:21:25 +02:00 | 
		
			
			
			
			
				| async.v | Fix tests/various/async FFL test | 2019-07-09 22:44:39 +02:00 | 
		
			
			
			
			
				| attrib05_port_conn.v | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. | 2019-06-04 10:42:42 +02:00 | 
		
			
			
			
			
				| attrib05_port_conn.ys | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. | 2019-06-04 10:42:42 +02:00 | 
		
			
			
			
			
				| attrib07_func_call.v | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. | 2019-06-04 10:42:42 +02:00 | 
		
			
			
			
			
				| attrib07_func_call.ys | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. | 2019-06-04 10:42:42 +02:00 | 
		
			
			
			
			
				| autoname.ys | autoname: add testcase with $-prefix-ed port | 2020-01-14 10:13:03 -08:00 | 
		
			
			
			
			
				| bug1480.ys | Fix #1462, #1480. | 2019-11-19 08:57:39 +01:00 | 
		
			
			
			
			
				| bug1496.ys | Fix #1496. | 2019-11-18 04:16:48 +01:00 | 
		
			
			
			
			
				| bug1531.ys | Add testcase | 2019-12-11 16:52:37 -08:00 | 
		
			
			
			
			
				| chparam.sh | Add tests/various/chparam.sh | 2019-05-06 16:03:15 +02:00 | 
		
			
			
			
			
				| constmsk_test.v | Added tests/various/constmsk_test.ys | 2014-09-04 15:07:30 +02:00 | 
		
			
			
			
			
				| constmsk_test.ys | Added tests/various/constmsk_test.ys | 2014-09-04 15:07:30 +02:00 | 
		
			
			
			
			
				| constmsk_testmap.v | Added tests/various/constmsk_test.ys | 2014-09-04 15:07:30 +02:00 | 
		
			
			
			
			
				| elab_sys_tasks.sv | Initial implementation of elaboration system tasks | 2019-05-03 03:10:43 +03:00 | 
		
			
			
			
			
				| elab_sys_tasks.ys | Initial implementation of elaboration system tasks | 2019-05-03 03:10:43 +03:00 | 
		
			
			
			
			
				| equiv_opt_multiclock.ys | Add equiv_opt -multiclock | 2019-09-11 13:55:59 +01:00 | 
		
			
			
			
			
				| gzip_verilog.v.gz | Add support for reading gzip'd input files | 2019-07-26 10:23:58 +01:00 | 
		
			
			
			
			
				| gzip_verilog.ys | Add support for reading gzip'd input files | 2019-07-26 10:23:58 +01:00 | 
		
			
			
			
			
				| help.ys | Add "help -all" and "help -celltypes" sanity test | 2020-01-28 18:11:34 -08:00 | 
		
			
			
			
			
				| hierarchy.sh | Fix tests | 2019-04-21 11:40:20 +02:00 | 
		
			
			
			
			
				| hierarchy_defer.ys | Expand test with `hierarchy' without -auto-top | 2019-09-03 12:17:26 -07:00 | 
		
			
			
			
			
				| mem2reg.ys | Do not propagate mem2reg attribute through to result | 2019-08-22 16:57:59 -07:00 | 
		
			
			
			
			
				| muxcover.ys | Merge origin/master | 2019-06-27 11:20:15 -07:00 | 
		
			
			
			
			
				| muxpack.v | Add more tests | 2019-06-21 12:31:04 -07:00 | 
		
			
			
			
			
				| muxpack.ys | Removal of more statcalls from tests | 2019-08-18 21:28:45 -07:00 | 
		
			
			
			
			
				| peepopt.ys | Use sat -tempinductand comments for why equiv_opt not sufficient | 2019-10-03 11:11:50 -07:00 | 
		
			
			
			
			
				| pmgen_reduce.ys | Add test for pmtest_test "reduce" demo pattern | 2019-08-17 14:05:10 +02:00 | 
		
			
			
			
			
				| pmux2shiftx.v | Add #1135 testcase | 2019-06-27 11:02:52 -07:00 | 
		
			
			
			
			
				| pmux2shiftx.ys | Add #1135 testcase | 2019-06-27 11:02:52 -07:00 | 
		
			
			
			
			
				| reg_wire_error.sv | Modified errors into warnings | 2018-06-05 18:03:22 +03:00 | 
		
			
			
			
			
				| reg_wire_error.ys | reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files | 2018-06-05 18:00:06 +03:00 | 
		
			
			
			
			
				| run-test.sh | Speed up "make test" and related cleanups | 2019-08-17 14:37:07 +02:00 | 
		
			
			
			
			
				| scratchpad.ys | add assert option to scratchpad command | 2019-12-16 14:00:21 +01:00 | 
		
			
			
			
			
				| script.ys | Update test for Pass::call_on_module() | 2019-07-02 08:22:31 -07:00 | 
		
			
			
			
			
				| shregmap.v | Add shregmap -tech xilinx test | 2019-06-12 08:34:06 -07:00 | 
		
			
			
			
			
				| shregmap.ys | Remove Xilinx test | 2019-08-22 16:18:07 -07:00 | 
		
			
			
			
			
				| signext.ys | Extend sign extension tests | 2019-06-20 12:43:59 -07:00 | 
		
			
			
			
			
				| specify.v | Fix tests/various/specify.v | 2019-07-03 11:25:05 +02:00 | 
		
			
			
			
			
				| specify.ys | Fix tests/various/specify.v | 2019-07-03 11:25:05 +02:00 | 
		
			
			
			
			
				| submod_extract.ys | Added tests/various/submod_extract.ys | 2014-07-26 17:22:18 +02:00 | 
		
			
			
			
			
				| svalways.sh | sv: Add tests for SV always types | 2019-11-21 21:06:28 +00:00 | 
		
			
			
			
			
				| wreduce.ys | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" | 2019-08-12 12:06:45 -07:00 | 
		
			
			
			
			
				| write_gzip.ys | Do not use Verific in tests/various/write_gzip.ys | 2019-08-16 14:22:46 +02:00 |