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Code Activity
yosys/techlibs/ice40
History
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
..
tests
.gitignore
abc9_hx.box Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_hx.lut Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_lp.box Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_lp.lut Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_model.v Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_u.box Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_u.lut Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
cells_sim.v Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
dsp_map.v
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc Do not overwrite LUT param 2019-08-28 18:46:53 -07:00
latches_map.v
Makefile.inc Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
synth_ice40.cc Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00