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yosys/backends/verilog
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whitequark 628437b01c verilog_backend: dump attributes on SwitchRule. 
This appears to be an omission.
2019-07-08 15:11:29 +00:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc verilog_backend: dump attributes on SwitchRule. 2019-07-08 15:11:29 +00:00