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Code Activity
yosys/frontends/ast
History
Clifford Wolf 6cc8e848b6 Fixed synthesis of functions in latched blocks
2013-05-16 16:44:06 +02:00
..
ast.cc Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00
ast.h Added nosync attribute and some async reset related fixes 2013-03-25 17:13:14 +01:00
genrtlil.cc Added nosync attribute and some async reset related fixes 2013-03-25 17:13:14 +01:00
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
simplify.cc Fixed synthesis of functions in latched blocks 2013-05-16 16:44:06 +02:00