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Code Activity
yosys/frontends/verilog
History
Zachary Snow 6b7267b849 verilog: fix multiple AST_PREFIX scope resolution issues 
- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
2021-09-21 12:10:59 -04:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
preproc.cc verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l verilog: Squash flex-triggered warning. 2021-09-13 18:58:17 +02:00
verilog_parser.y verilog: fix multiple AST_PREFIX scope resolution issues 2021-09-21 12:10:59 -04:00