whitequark 6a29e1f5b7 write_verilog: write RTLIL::Sa aka - as Verilog ?. ... Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.		2019-07-09 18:35:49 +00:00
..
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
verilog_backend.cc	write_verilog: write RTLIL::Sa aka - as Verilog ?.	2019-07-09 18:35:49 +00:00