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yosys/backends
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Benjamin Barzen 8611429237
ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2023-04-22 16:24:36 -07:00
..
aiger ABC9: Cell Port Bug Patch (#3670) 2023-04-22 16:24:36 -07:00
blif Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
btor sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
cxxrtl Add support for GHDL modfloor operator 2022-07-05 15:15:54 -04:00
edif Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
firrtl backends/firrtl: Ensure modInstance is valid 2023-02-03 08:27:52 -05:00
intersynth
jny Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
json Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
rtlil backends/rtlil: Do not shorten a value with z bits to 'x 2023-01-29 14:02:25 +01:00
simplec
smt2 yosys-smtbmc: support -h/--help (and exit with code 0). 2023-02-27 20:31:00 +00:00
smv Add bwmuxmap pass 2022-11-30 18:50:53 +01:00
spice
table
verilog verilog_backend: Do not run bwmuxmap even if in expr mode 2023-02-13 14:00:38 +01:00