yosys/tests/various/reg_wire_error.ys at 67005633e246e47683b11e13f08afb788bc9de02 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-06-04 05:11:22 +00:00

Udi Finkelstein 80d9d15f1c reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files

2018-06-05 18:00:06 +03:00

1 line

35 B

Text

Raw Blame History

read_verilog -sv reg_wire_error.sv