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aiger
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alumacc
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arch
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tests: remove unstable FPGA synthesis result checks
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2025-11-12 11:52:04 +01:00 |
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asicworld
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bind
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blif
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bram
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bugpoint
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raise_error: don't rely on module ordering in test
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2025-09-16 15:47:16 +02:00 |
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cxxrtl
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tests: replace CC and gcc with CXX and g++
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2025-09-11 16:50:23 +02:00 |
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errors
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fmt
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tests: replace CC and gcc with CXX and g++
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2025-09-11 16:50:23 +02:00 |
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fsm
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functional
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read_verilog: add -relativeshare for synthesis reproducibility testing
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2025-09-16 15:47:35 +02:00 |
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hana
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liberty
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libparse: fix quoting and negedge in filterlib -verilogsim
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2025-11-05 14:13:58 +01:00 |
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lut
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memfile
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memlib
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memories
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opt
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Merge pull request #3991 from adrianparvino/alumacc-sign
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2025-10-08 13:02:10 +02:00 |
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opt_share
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peepopt
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proc
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pyosys
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pyosys: fix regressions from 0.58
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2025-10-26 02:21:40 +03:00 |
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realmath
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rpc
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rtlil
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Add CONST_FLAG_UNSIZED
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2025-11-07 17:45:07 +13:00 |
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sat
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fix(parse): #5234 adjust width of rhs according to lhs
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2025-09-16 15:24:23 +02:00 |
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sdc
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sdc: add -keep_hierarchy test
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2025-11-19 15:26:02 +01:00 |
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select
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share
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sim
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Revert sim's cycle_width default back to 10, but keep -width option
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2025-10-20 14:40:05 +02:00 |
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simple
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simple_abc9
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smv
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sva
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svinterfaces
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tests/svinterfaces: re-chmod test script
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2025-10-15 09:49:53 +13:00 |
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svtypes
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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techmap
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Move global ABC configuration variables into AbcConfig and initialize them properly
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2025-11-05 13:56:04 +00:00 |
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tools
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tests: replace CC and gcc with CXX and g++
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2025-09-11 16:50:23 +02:00 |
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unit
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Optimize IdString operations to avoid calling c_str()
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2025-11-12 11:52:04 +01:00 |
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various
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sdc: add -keep_hierarchy test
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2025-11-19 15:26:02 +01:00 |
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verific
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Set port_id for Verific PortBus wires
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2025-10-23 20:51:53 +00:00 |
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verilog
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ignore generated file
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2025-11-17 13:35:38 +01:00 |
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vloghtb
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xprop
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.gitignore
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gen-tests-makefile.sh
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