Adrien Prost-Boucle 62196cbc0a Himbaechel for Xilinx uarch : Improve mapping of multiplexers ... - Add explicitly handling of A_WIDTH=1 for completeness - mux2 uses one LUT3 instead of a hard mux (which did use LUTs anyway) - mux4 uses one LUT4 instead of hard muxes (which did use LUTs anyway) - mux8 uses only bottom half of a slice - Add a mux12 for intermediate variant between mux8 and mux16 - For sizes larger than 16 inputs, instantiate the right mux size - More comments about implementation choices - More tests including with -widemux and -abc9, and more comments		2025-06-30 16:46:29 +02:00
..
memory_attributes	Fixing compiler warning/issues. Moving test script to the correct place	2019-12-16 10:23:45 -06:00
add_sub.v	Unify verilog style	2019-10-18 12:50:24 +02:00
adffs.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
blockram.v	Adding double_sync_ram_tdp to blockram.v	2023-12-04 15:52:03 +01:00
blockrom.v	tests: fix blockrom.v driver conflict	2024-12-02 16:56:42 +01:00
counter.v	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
dffs.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
fsm.v	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
latches.v	Unify verilog style	2019-10-18 12:50:24 +02:00
logic.v	Unify verilog style	2019-10-18 12:50:24 +02:00
lutram.v	Rename memory tests to lutram, add more xilinx tests	2019-12-12 17:44:37 -08:00
mul.v	intel_alm: Add multiply signedness to cells	2020-08-26 22:50:16 +02:00
mux.v	Himbaechel for Xilinx uarch : Improve mapping of multiplexers	2025-06-30 16:46:29 +02:00
shifter.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
tribuf.v	Unify verilog style	2019-10-18 12:50:24 +02:00