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yosys/tests/arch
Adrien Prost-Boucle 62196cbc0a Himbaechel for Xilinx uarch : Improve mapping of multiplexers
- Add explicitly handling of A_WIDTH=1 for completeness
- mux2 uses one LUT3 instead of a hard mux (which did use LUTs anyway)
- mux4 uses one LUT4 instead of hard muxes (which did use LUTs anyway)
- mux8 uses only bottom half of a slice
- Add a mux12 for intermediate variant between mux8 and mux16
- For sizes larger than 16 inputs, instantiate the right mux size
- More comments about implementation choices
- More tests including with -widemux and -abc9, and more comments
2025-06-30 16:46:29 +02:00
..
anlogic test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
common Himbaechel for Xilinx uarch : Improve mapping of multiplexers 2025-06-30 16:46:29 +02:00
ecp5 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
efinix test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
fabulous fabulous: Add support for mapping carry chains 2023-02-27 09:50:34 +01:00
gatemate test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
gowin test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
ice40 ice40_dsp: add test 2025-04-09 21:21:46 +03:00
intel_alm test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
machxo2 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
microchip test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
nanoxplore test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
nexus test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
quicklogic create duplicate IOFFs if multiple output ports are connected to the same register 2025-01-31 11:28:57 +01:00
xilinx Himbaechel for Xilinx uarch : Improve mapping of multiplexers 2025-06-30 16:46:29 +02:00
run-test.sh Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00