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yosys/tests/liberty/strangecolons.lib

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library (strange_colons) {
delay_model : "table_lookup";
simulation : false;
capacitive_load_unit (1,pF);
leakage_power_unit : "1pW";
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1v";
library_features : "report_delay_calculation";
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 30;
slew_lower_threshold_pct_fall : 30;
slew_upper_threshold_pct_rise : 70;
slew_upper_threshold_pct_fall : 70;
slew_derate_from_library : 1.0;
nom_process : 1.0;
nom_temperature : 85.0;
nom_voltage : 0.75;
cell(strange_colons) {
sensitization_master : sensitization_3pins ;
area : 0.1 ;
dont_touch : true ;
dont_use : true ;
pin(A) {
capacitance : 0.0001 ;
direction : input ;
driver_waveform_rise : "driver_waveform_default_rise" ;
driver_waveform_fall : "driver_waveform_default_fall" ;
fall_capacitance : 0.0001 ;
input_voltage : default ;
max_transition : 0.1 ;
related_ground_pin : VSS ;
related_power_pin : VDD ;
rise_capacitance : 0.0001 ;
active_input_ccb(strange_colons:ck);
active_input_ccb(strange_colons:d, \
strange_colons:d);
propagating_ccb(strange_colons:a, strange_colons:y);
input_ccb(strange_colons:a) {
is_needed : true ;
is_inverting : true ;
miller_cap_fall : 0.0001 ;
miller_cap_rise : 1e-05 ;
stage_type : both ;
}
}
}
}