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124 lines
3.1 KiB
Verilog
124 lines
3.1 KiB
Verilog
// File: design.v
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// Generated by MyHDL 0.8
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// Date: Tue Dec 3 04:33:14 2013
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module d (
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cos_z0,
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sin_z0,
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done,
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z0,
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start,
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clock,
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reset
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);
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// Sine and cosine computer.
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//
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// This module computes the sine and cosine of an input angle. The
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// floating point numbers are represented as integers by scaling them
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// up with a factor corresponding to the number of bits after the point.
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//
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// Ports:
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// -----
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// cos_z0: cosine of the input angle
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// sin_z0: sine of the input angle
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// done: output flag indicated completion of the computation
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// z0: input angle
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// start: input that starts the computation on a posedge
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// clock: clock input
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// reset: reset input
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output signed [19:0] cos_z0;
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reg signed [19:0] cos_z0;
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output signed [19:0] sin_z0;
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reg signed [19:0] sin_z0;
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output done;
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reg done;
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input signed [19:0] z0;
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input start;
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input clock;
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input reset;
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(* gentb_constant = 1'b0 *)
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wire reset;
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always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR
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reg [5-1:0] i;
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reg [1-1:0] state;
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reg signed [20-1:0] dz;
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reg signed [20-1:0] dx;
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reg signed [20-1:0] dy;
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reg signed [20-1:0] y;
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reg signed [20-1:0] x;
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reg signed [20-1:0] z;
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if (reset) begin
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state = 1'b0;
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cos_z0 <= 1;
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sin_z0 <= 0;
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done <= 1'b0;
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x = 0;
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y = 0;
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z = 0;
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i = 0;
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end
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else begin
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case (state)
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1'b0: begin
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if (start) begin
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x = 159188;
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y = 0;
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z = z0;
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i = 0;
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done <= 1'b0;
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state = 1'b1;
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end
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end
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1'b1: begin
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dx = $signed(y >>> $signed({1'b0, i}));
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dy = $signed(x >>> $signed({1'b0, i}));
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case (i)
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0: dz = 205887;
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1: dz = 121542;
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2: dz = 64220;
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3: dz = 32599;
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4: dz = 16363;
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5: dz = 8189;
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6: dz = 4096;
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7: dz = 2048;
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8: dz = 1024;
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9: dz = 512;
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10: dz = 256;
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11: dz = 128;
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12: dz = 64;
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13: dz = 32;
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14: dz = 16;
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15: dz = 8;
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16: dz = 4;
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17: dz = 2;
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default: dz = 1;
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endcase
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if ((z >= 0)) begin
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x = x - dx;
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y = y + dy;
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z = z - dz;
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end
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else begin
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x = x + dx;
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y = y - dy;
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z = z + dz;
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end
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if ((i == (19 - 1))) begin
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cos_z0 <= x;
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sin_z0 <= y;
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state = 1'b0;
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done <= 1'b1;
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end
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else begin
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i = i + 1;
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end
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end
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endcase
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end
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end
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endmodule
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