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yosys/kernel
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Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL 
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
..
bitpattern.h Removed unnecessary cast. 2015-09-01 12:40:36 +02:00
calc.cc Fix mingw compile issue (2nd attempt) 2017-02-23 14:21:02 +01:00
cellaigs.cc kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
cellaigs.h Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
celledges.cc kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
celledges.h Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
celltypes.h kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
consteval.h kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
constids.inc verific: do not assert if wire not found; warn instead 2020-04-23 16:28:11 -07:00
cost.h Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) 2019-08-11 11:39:46 +02:00
driver.cc Add YS_ prefix to macros, add explanation and apply to older version as well 2020-03-13 17:19:54 +01:00
hashlib.h Merge pull request #1969 from boqwxp/pool_emplace 2020-04-22 12:10:42 -07:00
log.cc Add YS_ prefix to macros, add explanation and apply to older version as well 2020-03-13 17:19:54 +01:00
log.h Hole value recovery and specialization implementation for qbfsat command. 2020-04-04 22:13:25 +00:00
macc.h kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
modtools.h Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 2020-04-02 07:13:33 -07:00
register.cc Use script-style heredoc syntax for REPL heredocs. 2020-04-15 16:15:51 +00:00
register.h Add ScriptPass::run_nocheck and use for abc9 2020-03-09 14:34:22 +00:00
rtlil.cc Preserve 'signed'-ness of a verilog wire through RTLIL 2020-04-27 09:44:24 -07:00
rtlil.h Preserve 'signed'-ness of a verilog wire through RTLIL 2020-04-27 09:44:24 -07:00
satgen.h kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
sigtools.h kernel: const Wire* overload -> Wire* !!! 2020-03-26 16:21:30 -07:00
timinginfo.h kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
utils.h Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
yosys.cc Support custom PROGRAM_PREFIX 2020-04-10 10:38:40 +02:00
yosys.h Merge pull request #1894 from YosysHQ/mingw_fix 2020-04-15 17:43:31 +02:00