mirror of
https://github.com/YosysHQ/yosys
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f42923d896
Neither is a cell anything implements. They exist so a mapping rule can
re-emit a multiplier without matching itself, and a later techmap or
`chtype` consumes them. Nothing ever declared them, so
`Cell::port_dir()` fell through to PD_UNKNOWN for every port, and
anything that has to tell a cell's inputs from its outputs had to guess.
signorm guesses "output": setup_driven_wires() skips only PD_INPUT, so
\A and \B of a $__mul are read as drivers. \B is the enclosing module's
own input, already driven by its $input_port cell, and \A is a slice, so
both take the fallback -- interpose a helper wire and connect it -- and
both sides then look driven, which is what a $connect means. _80_mul's
wide branch has two $__mul instances, and it runs `proc; clean` through
_TECHMAP_DO_, whose closing opt_expr normalizes the map design. Result:
four helper wires and four $connect cells manufactured out of a design
that has no multi-driver net in it anywhere.
Declaring them as blackboxes gives the interface a definition without
making them mappable: techmap skips blackbox templates outright
(`tpl->get_blackbox_attribute(ignore_wb)`), and every rule that emits
these types carries an explicit techmap_celltype, so nothing was relying
on matching them by module name.
96deee136 stopped the $connect cells escaping the index, which is right
regardless; this stops them being created. `make -C tests` is unchanged
at 7 failures.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
363 lines
10 KiB
Verilog
363 lines
10 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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* 2019 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* Tech-mapping rules for decomposing arbitrarily-sized $mul cells
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* into an equivalent collection of smaller `DSP_NAME cells (with the
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* same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
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* to $shl and $add cells.
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*
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*/
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`ifndef DSP_A_MAXWIDTH
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$fatal(1, "Macro DSP_A_MAXWIDTH must be defined");
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`endif
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`ifndef DSP_B_MAXWIDTH
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$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
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`endif
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`ifndef DSP_B_MAXWIDTH
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$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
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`endif
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`ifndef DSP_A_MAXWIDTH_PARTIAL
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`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH
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`endif
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`ifndef DSP_B_MAXWIDTH_PARTIAL
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`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH
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`endif
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`ifndef DSP_NAME
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$fatal(1, "Macro DSP_NAME must be defined");
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`endif
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`define MAX(a,b) (a > b ? a : b)
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`define MIN(a,b) (a < b ? a : b)
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// $__mul and $__soft_mul are not cells anything implements: the rules below
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// re-emit a multiplier as one of them so that the match does not recurse into
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// itself, and a later techmap or `chtype` consumes them. Nothing declared them,
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// so port_dir() answered PD_UNKNOWN for their ports, and anything that has to
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// tell a cell's inputs from its outputs then has to guess -- the signorm index
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// guesses "output", reads A and B as drivers, and manufactures a multi-driver
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// conflict on every net feeding one. Give the interface a definition instead.
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//
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// The blackbox attribute is what keeps techmap from taking these as mapping
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// templates: it skips blackbox templates outright, so they stay pure
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// declarations. Every rule that produces them carries an explicit
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// techmap_celltype, so nothing depends on matching by module name here.
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(* blackbox *)
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module \$__mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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endmodule
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(* blackbox *)
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module \$__soft_mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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endmodule
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(* techmap_celltype = "$mul $__mul" *)
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module _80_mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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generate
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if (0) begin end
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`ifdef DSP_A_MINWIDTH
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else if (A_WIDTH < `DSP_A_MINWIDTH)
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wire _TECHMAP_FAIL_ = 1;
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`endif
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`ifdef DSP_B_MINWIDTH
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else if (B_WIDTH < `DSP_B_MINWIDTH)
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wire _TECHMAP_FAIL_ = 1;
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`endif
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`ifdef DSP_Y_MINWIDTH
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else if (Y_WIDTH < `DSP_Y_MINWIDTH)
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wire _TECHMAP_FAIL_ = 1;
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`endif
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`ifdef DSP_SIGNEDONLY
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else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED)
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\$mul #(
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.A_SIGNED(1),
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.B_SIGNED(1),
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.A_WIDTH(A_WIDTH + 1),
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.B_WIDTH(B_WIDTH + 1),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A({1'b0, A}),
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.B({1'b0, B}),
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.Y(Y)
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);
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`endif
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else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
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\$mul #(
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(B_WIDTH),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(B),
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.B(A),
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.Y(Y)
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);
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else begin
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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`ifdef DSP_SIGNEDONLY
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localparam sign_headroom = 1;
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`else
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localparam sign_headroom = 0;
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`endif
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genvar i;
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if (A_WIDTH > `DSP_A_MAXWIDTH) begin
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localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
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localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
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localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
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localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
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if (A_SIGNED && B_SIGNED) begin : blk
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(* force_downto *)
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wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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wire signed [last_Y_WIDTH-1:0] last_partial;
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(* force_downto *)
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wire signed [Y_WIDTH-1:0] partial_sum [n:0];
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end
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else begin : blk
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(* force_downto *)
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wire [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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wire [last_Y_WIDTH-1:0] last_partial;
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(* force_downto *)
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wire [Y_WIDTH-1:0] partial_sum [n:0];
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end
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for (i = 0; i < n; i=i+1) begin:sliceA
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\$__mul #(
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.A_SIGNED(sign_headroom),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(partial_Y_WIDTH)
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) mul (
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.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
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.B(B),
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.Y(blk.partial[i])
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);
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// TODO: Currently a 'cascade' approach to summing the partial
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// products is taken here, but a more efficient 'binary
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// reduction' approach also exists...
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if (i == 0)
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assign blk.partial_sum[i] = blk.partial[i];
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else
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assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
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end
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(last_A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(last_Y_WIDTH)
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) sliceA.last (
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.A(A[A_WIDTH-1 -: last_A_WIDTH]),
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.B(B),
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.Y(blk.last_partial)
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);
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assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
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assign Y = blk.partial_sum[n];
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end
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else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
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localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
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localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
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localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
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localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
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if (A_SIGNED && B_SIGNED) begin : blk
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(* force_downto *)
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wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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wire signed [last_Y_WIDTH-1:0] last_partial;
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(* force_downto *)
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wire signed [Y_WIDTH-1:0] partial_sum [n:0];
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end
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else begin : blk
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(* force_downto *)
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wire [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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wire [last_Y_WIDTH-1:0] last_partial;
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(* force_downto *)
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wire [Y_WIDTH-1:0] partial_sum [n:0];
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end
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for (i = 0; i < n; i=i+1) begin:sliceB
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(sign_headroom),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),
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.Y_WIDTH(partial_Y_WIDTH)
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) mul (
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.A(A),
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.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
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.Y(blk.partial[i])
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);
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// TODO: Currently a 'cascade' approach to summing the partial
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// products is taken here, but a more efficient 'binary
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// reduction' approach also exists...
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if (i == 0)
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assign blk.partial_sum[i] = blk.partial[i];
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else
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assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
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end
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(last_B_WIDTH),
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.Y_WIDTH(last_Y_WIDTH)
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) mul_sliceB_last (
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.A(A),
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.B(B[B_WIDTH-1 -: last_B_WIDTH]),
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.Y(blk.last_partial)
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);
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assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
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assign Y = blk.partial_sum[n];
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end
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else begin
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if (A_SIGNED) begin : blkA
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wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
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end
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else begin : blkA
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wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
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end
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if (B_SIGNED) begin : blkB
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wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
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end
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else begin : blkB
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wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
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end
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`DSP_NAME #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH),
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.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
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) _TECHMAP_REPLACE_ (
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.A(blkA.Aext),
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.B(blkB.Bext),
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.Y(Y)
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);
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end
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end
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endgenerate
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endmodule
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(* techmap_celltype = "$mul $__mul" *)
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module _90_soft_mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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// Indirection necessary since mapping
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// back to $mul will cause recursion
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generate
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if (A_SIGNED && !B_SIGNED)
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\$__soft_mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(1),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH+1),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B({1'b0,B}),
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.Y(Y)
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);
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else if (!A_SIGNED && B_SIGNED)
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\$__soft_mul #(
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.A_SIGNED(1),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH+1),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A({1'b0,A}),
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.B(B),
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.Y(Y)
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);
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else
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\$__soft_mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.Y(Y)
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);
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endgenerate
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endmodule
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