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The library file is the only description of these cell types, so unless the user has separately read in a model, memory_libmap left the design instantiating a module that does not exist. `hierarchy -check` rejects that, and Cell::port_dir() has nothing to answer with, which matters beyond tidiness: setPort treats a port of unknown direction as an output, so on a normalized design every input port gets a fresh driven wire plus a $connect cell tying it back to its real source. Those reach the backend -- write_verilog emits them as `tran` -- and simulate as x. Declare each port on a generated blackbox before connecting it, following memory_bram. Directions come from the cell interface in memlib.md, where PORT_<name>_RD_DATA is the sole output; widths come from the signal being connected, so they match the chosen configuration. A model the user supplied is left alone rather than reshaped. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo |
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| .. | ||
| CMakeLists.txt | ||
| memlib.cc | ||
| memlib.h | ||
| memlib.md | ||
| memory.cc | ||
| memory_bmux2rom.cc | ||
| memory_bram.cc | ||
| memory_collect.cc | ||
| memory_dff.cc | ||
| memory_libmap.cc | ||
| memory_map.cc | ||
| memory_memx.cc | ||
| memory_narrow.cc | ||
| memory_nordff.cc | ||
| memory_share.cc | ||
| memory_unpack.cc | ||