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memory_bram: intern generated blackbox names as public twines

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load_blackbox() created the module and its port wires with
twines.add(Twine{...}), which interns a private twine, while
load_blackboxes() checked for an existing module with
twines.add(std::string{...}), which interns a public one. The two never
matched, so the generated modules were unreachable under the name the
emitted cells use for their type: write_rtlil showed the module as
$priv@... against a $pub@... cell type.

The blackboxes were therefore inert since 25e7118e4 introduced them.
Cell::port_dir() kept falling back to PD_UNKNOWN for every BRAM cell,
which is the thing that commit set out to fix, and `hierarchy -check`
still had no module to find.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
This commit is contained in:
Emil J. Tywoniak 2026-07-21 14:00:05 +02:00
parent 7617dae629
commit 0768897fd9
1 changed files with 3 additions and 3 deletions
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6
passes/memory/memory_bram.cc
View file

@ -157,19 +157,19 @@ struct rules_t
}
log_debug("setting up %s\n", name);
Module* mod = design->addModule(design->twines.add(Twine{name.str()}));
Module* mod = design->addModule(design->twines.add(std::string{name.str()}));
mod->set_bool_attribute(ID::blackbox);
for (auto [name, width] : inputs)
{
log_debug("input %s width %d\n", name.c_str(), width);
mod->addWire(design->twines.add(Twine{name.str()}), width)->port_input = true;
mod->addWire(design->twines.add(std::string{name.str()}), width)->port_input = true;
}
for (auto [name, width] : outputs)
{
log_debug("output %s width %d\n", name.c_str(), width);
mod->addWire(design->twines.add(Twine{name.str()}), width)->port_output = true;
mod->addWire(design->twines.add(std::string{name.str()}), width)->port_output = true;
}
mod->fixup_ports();