mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-24 12:07:53 +00:00
Code Activity
yosys/frontends/verilog
History
Emil J 588c5d5a57
verilog_lexer: remove comment 
Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-07-19 22:46:17 +02:00
..
.gitignore read_verilog, ast: use unified locations in errors and simplify dependencies 2025-07-10 21:15:50 +02:00
const2ast.cc ast, read_verilog: unify location types, reduce filename copying 2025-07-10 21:15:50 +02:00
Makefile.inc verilog: fix build dependency graph 2025-07-10 23:59:54 +02:00
preproc.cc preproc.cc: Use full path for generated file 2025-07-10 21:15:50 +02:00
preproc.h preproc: formatting 2025-07-19 22:45:19 +02:00
verilog_error.cc read_verilog, ast: use unified locations in errors and simplify dependencies 2025-07-10 21:15:50 +02:00
verilog_error.h read_verilog, ast: use unified locations in errors and simplify dependencies 2025-07-10 21:15:50 +02:00
verilog_frontend.cc read_verilog, ast: use unified locations in errors and simplify dependencies 2025-07-10 21:15:50 +02:00
verilog_frontend.h fixup! fixup! ast, read_verilog: unify location types, reduce filename copying 2025-07-10 21:15:50 +02:00
verilog_lexer.h read_verilog, ast: use unified locations in errors and simplify dependencies 2025-07-10 21:15:50 +02:00
verilog_lexer.l verilog_lexer: remove comment 2025-07-19 22:46:17 +02:00
verilog_location.h fixup! ast, read_verilog: unify location types, reduce filename copying 2025-07-10 21:15:50 +02:00
verilog_parser.y read_verilog, ast: use unified locations in errors and simplify dependencies 2025-07-10 21:15:50 +02:00