mirror of
https://github.com/YosysHQ/yosys
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| .. | ||
| .gitignore | ||
| blackbox.ys | ||
| blackbox_empty.ys | ||
| blackbox_ql.ys | ||
| bounds.sv | ||
| bounds.vhd | ||
| bounds.ys.DISABLED | ||
| case.sv | ||
| case.ys | ||
| clocking.ys | ||
| enum_values.sv | ||
| enum_values.ys | ||
| memory_semantics.ys.DISABLED | ||
| range_case.sv | ||
| range_case.ys | ||
| README.md | ||
| rom_case.ys.DISABLED | ||
| run-test.sh | ||
| setenv.flist | ||
| setenv.ys | ||
Verific Test Cases
Disabled
bounds: checks top and bottom bound attributes, which are removed to avoid OpenSTA issuesmemory_semantics: relies on initial values being retained, which we do not wantrom_case: relies on using Verific's VHDL frontend rather than GHDL