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65 lines
1.1 KiB
Verilog
65 lines
1.1 KiB
Verilog
module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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wire [8:0] soa;
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wire [8:0] sob;
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MULT9X9 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.SIA(8'b0),
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.SIB(8'b0),
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.ASIGN(A_SIGNED),
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.BSIGN(B_SIGNED),
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.ASEL(1'b0),
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.BSEL(1'b0),
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.SOA(soa),
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.SOB(sob),
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.DOUT(Y)
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);
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endmodule
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module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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wire [17:0] soa;
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wire [17:0] sob;
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MULT18X18 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.SIA(18'b0),
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.SIB(18'b0),
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.ASIGN(A_SIGNED),
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.BSIGN(B_SIGNED),
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.ASEL(1'b0),
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.BSEL(1'b0),
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.SOA(soa),
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.SOB(sob),
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.DOUT(Y)
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);
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endmodule
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module \$__MUL36X36 (input [35:0] A, input [35:0] B, output [72:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 36;
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parameter Y_WIDTH = 72;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT36X36 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.ASIGN(A_SIGNED),
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.BSIGN(B_SIGNED),
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.DOUT(Y)
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);
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endmodule
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