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yosys/techlibs/gowin
History
Priit Laes 5ad9e4cacc gowin: dsp: Add basic DSP block inferencing for various MULT cells
2025-10-08 16:39:37 +03:00
..
arith_map.v gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
brams.txt gowin: Change BYTE ENABLE handling. 2024-01-27 17:19:49 +10:00
brams_map.v gowin: Fix SDP write enable port. 2024-01-30 17:06:59 +10:00
cells_map.v iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
cells_sim.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra.py Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw1n.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw2a.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw5a.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
dsp_map.v gowin: dsp: Add basic DSP block inferencing for various MULT cells 2025-10-08 16:39:37 +03:00
lutrams.txt gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Makefile.inc gowin: dsp: Add basic DSP block inferencing for various MULT cells 2025-10-08 16:39:37 +03:00
synth_gowin.cc gowin: dsp: Add basic DSP block inferencing for various MULT cells 2025-10-08 16:39:37 +03:00