Emil J. Tywoniak c3ffbf6fae WIP		2026-06-12 00:18:53 +02:00
..
choices
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc
mul2dsp.v
opensta.cc	WIP	2026-06-12 00:18:53 +02:00
opensta.h	opensta: refactor default command	2025-11-19 15:20:50 +01:00
pmux2mux.v
prep.cc	Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.	2026-01-23 01:14:35 +00:00
sdc_expand.cc	opensta, sdc_expand: mark as experimental	2025-11-19 15:31:17 +01:00
simcells.v	simcells: $dffsr and derivatives undefine S&R in logic tables	2026-03-19 19:27:30 +01:00
simlib.v	WIP	2026-06-10 19:22:53 +02:00
smtmap.v
synth.cc	Add check before flatten in synth_*.	2026-05-05 14:06:58 +02:00
techmap.v	WIP	2026-06-10 14:52:50 +02:00