Akash Levy ccc2ba41f2 Merge branch 'YosysHQ:main' into main		2025-05-12 15:02:55 -07:00
..
aiger
alumacc	macc_v2: Add test	2025-01-27 13:19:26 +01:00
arch	URAM mapping : Add test for 2048 x 144b	2025-05-10 14:53:56 +02:00
asicworld
bind
blif	Changed boolopt naming	2025-01-16 19:36:27 -08:00
bram
cxxrtl	Reinstate #4768	2025-04-08 11:58:05 +12:00
errors
fmt
fsm
functional
hana
liberty	liberty: fix tests	2025-04-23 20:20:43 +00:00
lut
memfile
memlib	fixes for the yosys test	2025-03-27 17:19:08 -07:00
memories
opt	Merge branch 'YosysHQ:main' into main	2025-04-28 18:12:42 -07:00
opt_share
peepopt	added new muxorder tests	2025-05-08 14:05:13 -07:00
proc
realmath
rpc
sat	share: Cleanup and additional testing	2025-04-15 12:34:46 +02:00
select	design.cc: Fix selections when copying	2025-04-08 16:35:12 +12:00
share
silimate	finalized tests	2025-05-11 11:16:50 -07:00
sim	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
simple	Final cleanup	2025-02-14 10:18:13 -08:00
simple_abc9	Reinstate #4768	2025-04-08 11:58:05 +12:00
smv
sva
svinterfaces
svtypes	Sync	2024-12-19 21:40:30 -08:00
techmap	Merge upstream yosys	2025-04-21 17:36:24 -07:00
tools
unit	rtlil: Add {from,to}_hdl_index methods to Wire	2025-02-18 17:08:45 +01:00
various	Merge branch 'YosysHQ:main' into main	2025-04-28 13:57:29 -07:00
verific	Revert clocking.ys	2025-02-13 20:32:17 -08:00
verilog	tests: Add default param test file	2025-05-05 10:18:52 +12:00
vloghtb
xprop
gen-tests-makefile.sh	Update gen-tests-makefile.sh	2025-03-27 10:33:51 +13:00