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yosys/tests/verilog
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Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
2021-10-25 18:25:50 -07:00
..
.gitignore
absurd_width.ys
absurd_width_const.ys
atom_type_signedness.ys
block_end_label_only.ys sv: fix up end label checking 2021-06-16 21:48:05 -04:00
block_end_label_wrong.ys sv: fix up end label checking 2021-06-16 21:48:05 -04:00
block_labels.ys
bug656.v
bug656.ys
bug2037.ys
bug2042-sv.ys
bug2042.ys
bug2493.ys
conflict_assert.ys
conflict_cell_memory.ys
conflict_interface_port.ys
conflict_memory_wire.ys
conflict_pwire.ys
conflict_wire_memory.ys
const_arst.ys
const_sr.ys
delay_mintypmax.ys
delay_risefall.ys
for_decl_no_init.ys sv: support declaration in procedural for initialization 2021-08-30 15:19:21 -06:00
for_decl_no_sv.ys sv: support declaration in procedural for initialization 2021-08-30 15:19:21 -06:00
for_decl_shadow.sv sv: support declaration in procedural for initialization 2021-08-30 15:19:21 -06:00
for_decl_shadow.ys sv: support declaration in procedural for initialization 2021-08-30 15:19:21 -06:00
func_arg_mismatch_1.ys
func_arg_mismatch_2.ys
func_arg_mismatch_3.ys
func_arg_mismatch_4.ys
func_typename_ret.sv sv: allow typenames as function return types 2021-03-19 12:08:43 -04:00
func_typename_ret.ys sv: allow typenames as function return types 2021-03-19 12:08:43 -04:00
gen_block_end_label_only.ys sv: fix up end label checking 2021-06-16 21:48:05 -04:00
gen_block_end_label_wrong.ys sv: fix up end label checking 2021-06-16 21:48:05 -04:00
genblk_case.v
genblk_case.ys
genblk_port_decl.ys
genfor_decl_no_init.ys sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
genfor_decl_no_sv.ys sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
genvar_loop_decl_1.sv sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
genvar_loop_decl_1.ys sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
genvar_loop_decl_2.sv sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
genvar_loop_decl_2.ys sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
genvar_loop_decl_3.sv sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
genvar_loop_decl_3.ys sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
global_parameter.ys
hidden_decl.ys
ifdef_nest.ys preproc: test coverage for #2712 2021-03-30 12:23:18 -04:00
ifdef_unterminated.ys preproc: test coverage for #2712 2021-03-30 12:23:18 -04:00
include_self.v
include_self.ys
int_types.sv
int_types.ys
localparam_no_default_1.ys
localparam_no_default_2.ys
macro_arg_tromp.sv verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
macro_arg_tromp.ys verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
macro_unapplied.ys
macro_unapplied_newline.ys
mem_bounds.sv mem2reg: tolerate out of bounds constant accesses 2021-06-08 15:02:57 -04:00
mem_bounds.ys mem2reg: tolerate out of bounds constant accesses 2021-06-08 15:02:57 -04:00
module_end_label.ys sv: fix up end label checking 2021-06-16 21:48:05 -04:00
net_types.sv sv: support wand and wor of data types 2021-09-21 14:52:28 -04:00
net_types.ys sv: support wand and wor of data types 2021-09-21 14:52:28 -04:00
package_end_label.ys sv: check validity of package end label 2021-05-10 14:37:32 -04:00
package_task_func.sv sv: support tasks and functions within packages 2021-06-01 13:17:41 -04:00
package_task_func.ys sv: support tasks and functions within packages 2021-06-01 13:17:41 -04:00
param_int_types.sv
param_int_types.ys
param_no_default.sv
param_no_default.ys
param_no_default_not_svmode.ys
param_no_default_unbound_1.ys
param_no_default_unbound_2.ys
param_no_default_unbound_3.ys
param_no_default_unbound_4.ys
param_no_default_unbound_5.ys
parameters_across_files.ys sv: allow globals in one file to depend on globals in another 2021-03-12 11:22:41 -05:00
port_int_types.sv
port_int_types.ys
prefix.sv verilog: fix multiple AST_PREFIX scope resolution issues 2021-09-21 12:10:59 -04:00
prefix.ys verilog: fix multiple AST_PREFIX scope resolution issues 2021-09-21 12:10:59 -04:00
run-test.sh
struct_access.sv sv: fix two struct access bugs 2021-07-15 11:57:20 -04:00
struct_access.ys sv: fix two struct access bugs 2021-07-15 11:57:20 -04:00
task_attr.ys
typedef_across_files.ys sv: carry over global typedefs from previous files 2021-03-17 15:53:52 -04:00
typedef_legacy_conflict.ys sv: carry over global typedefs from previous files 2021-03-17 15:53:52 -04:00
unbased_unsized.sv
unbased_unsized.ys
unbased_unsized_tern.sv verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
unbased_unsized_tern.ys verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
unmatched_else.ys
unmatched_elsif.ys
unmatched_endif.ys
unmatched_endif_2.ys preproc: test coverage for #2712 2021-03-30 12:23:18 -04:00
unnamed_block.ys
unnamed_genblk.sv
unnamed_genblk.ys
upto.ys
wire_and_var.sv
wire_and_var.ys