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yosys/frontends/ast
Rupert Swarbrick 51ed4a7149 Use range-based for loop in AST::process
No functional change: just get rid of the explicit iterator and
replace (*it)-> with child->. It's even the same number of characters,
but is hopefully a little easier to read.
2021-05-13 23:37:27 -04:00
..
ast.cc Use range-based for loop in AST::process 2021-05-13 23:37:27 -04:00
ast.h verilog: Use proc memory writes in the frontend. 2021-03-08 20:16:29 +01:00
dpicall.cc dpi: Support for chandle type 2021-01-23 22:24:31 +00:00
genrtlil.cc verilog: Use proc memory writes in the frontend. 2021-03-08 20:16:29 +01:00
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
simplify.cc verilog: fix buf/not primitives with multiple outputs 2021-03-17 11:44:03 -04:00