mirror of
https://github.com/YosysHQ/yosys
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116 lines
No EOL
4 KiB
C++
116 lines
No EOL
4 KiB
C++
/**
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* Generalized compressor-tree utilities for multi-operand addition
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*
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* Terminology:
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* - compressor: $fa viewed as reducing N inputs to M outputs (sum + shifted carry) (N:M compressor)
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* - level: A stage of parallel compression operations
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* - depth: Maximum number of N:M compressor levels from any input to a signal
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*
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* Supported compressors:
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* - 3:2 compressor
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* - 4:2 compressor
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*
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* References:
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* - "Some schemes for parallel multipliers" (https://www.acsel-lab.com/arithmetic/arith6/papers/ARITH6_Dadda.pdf)
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* - "Binary Adder Architectures for Cell-Based VLSI" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
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* - "Basilisk: Achieving Competitive Performance with Open EDA Tools" (https://arxiv.org/pdf/2405.03523)
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* - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
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* - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
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*/
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#ifndef COMPRESSOR_TREE_H
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#define COMPRESSOR_TREE_H
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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namespace CompressorTree
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{
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// Width threshold below which a ripple is preferred over parallel-prefix
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constexpr int RIPPLE_PREFIX_THRESHOLD = 16;
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enum class Strategy {
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FA_ONLY, // 3:2 compressors
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PREFER_42, // Prefer 4:2 grouping when >=4 operands ready
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DADDA, // Defer compression until column counts exceed
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};
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struct DepthSig {
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SigSpec sig;
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int depth;
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};
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enum class FinalAdder {
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DEFAULT, // emit $add and let downstream techmap pick
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RIPPLE, // emit $add with explicit narrow hint
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PARALLEL_PREFIX, // emit $add with PARALLEL_PREFIX
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};
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enum class FinalMode {
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AUTO,
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RIPPLE,
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PREFIX,
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};
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std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
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std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
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SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width);
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/**
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* generate_partial_products() - Generate partial products for FMA concat
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* @module:The Yosys module to which the compressors will be added
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* @a: Signal A
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* @b: Signal B
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* @a_signed: Whether signal A is signed
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* @b_signed: Whether signal B is signed
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* @width: Target width
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*
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* Return: Partial-product matrix as a set of depth-0 vectors
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*/
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std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width);
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/**
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* reduce_scheduled() - Reduce multiple operands to two using a compressor tree
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* @module: The Yosys module to which the compressors will be added
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* @operands: Vector of operands to be reduced
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* @sigs: Vector of input signals (operands) to be reduced
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* @width: Target bit-width to which all operands will be zero-extended
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* @strategy: Compression strategy to use
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* @compressor_count: Optional pointer to return the number of $fa cells emitted
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*
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* Return: The final two reduced operands, that are to be fed into an adder
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*/
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std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count = nullptr);
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/**
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* emit_kogge_stone() - Emit a Kogge-Stone parallel-prefix adder
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* @module: The Yosys module to which the gates will be added
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* @a: Signal A
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* @b: Signal B
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* @y: Signal Y = (A + B) mod 2^W
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*/
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void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y);
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/**
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* emit_final_adder() - Emit the final carry-propagate addition between the two reduced vectors
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* @module:The Yosys module to which the compressors will be added
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* @a: Signal A
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* @b: Signal B
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* @y: Signal Y
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* @choice: Adder type to instantiate
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*
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* Return: Cell* of the emitted instance
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*/
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Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice);
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FinalAdder pick_final_adder(int width, FinalMode mode);
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} // namespace CompressorTree
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YOSYS_NAMESPACE_END
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#endif // COMPRESSOR_TREE_H
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