mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-25 11:26:22 +00:00
Cleanup.
This commit is contained in:
nella
parent
932be8c611
commit
4eee3e9e4f
3 changed files with 343 additions and 318 deletions
2
Makefile
2
Makefile
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@ -671,7 +671,7 @@ OBJS += kernel/log_compat.o
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endif
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OBJS += kernel/binding.o kernel/tclapi.o
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OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o
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OBJS += kernel/drivertools.o kernel/functional.o kernel/threading.o
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OBJS += kernel/drivertools.o kernel/functional.o kernel/threading.o kernel/compressor_tree.o
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ifeq ($(ENABLE_ZLIB),1)
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OBJS += kernel/fstdata.o
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endif
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334
kernel/compressor_tree.cc
Normal file
334
kernel/compressor_tree.cc
Normal file
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@ -0,0 +1,334 @@
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#include "compressor_tree.h"
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YOSYS_NAMESPACE_BEGIN
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namespace CompressorTree
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{
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std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
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{
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec cout = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, a, b, c, cout, sum);
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SigSpec carry;
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carry.append(State::S0);
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carry.append(cout.extract(0, width - 1));
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return {sum, carry};
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}
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std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width)
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{
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// First FA: a + b + c -> s0
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SigSpec s0 = module->addWire(NEW_ID, width);
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SigSpec cout_h_full = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, a, b, c, cout_h_full, s0);
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// cin[0] = 0, cin[i] = cout_h_full[i-1]
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SigSpec cin;
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cin.append(State::S0);
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if (width > 1)
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cin.append(cout_h_full.extract(0, width - 1));
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// Second FA: s0 + d + cin -> sum
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec carry_full = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, s0, d, cin, carry_full, sum);
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SigSpec carry;
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carry.append(State::S0);
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if (width > 1)
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carry.append(carry_full.extract(0, width - 1));
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return {sum, carry};
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}
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SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
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{
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// Zero/sign-extend to width
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if (GetSize(sig) < width) {
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SigBit pad;
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if (is_signed && GetSize(sig) > 0)
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pad = sig[GetSize(sig) - 1];
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else
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pad = State::S0;
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sig.append(SigSpec(pad, width - GetSize(sig)));
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}
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// Truncate to width
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if (GetSize(sig) > width)
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sig = sig.extract(0, width);
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return sig;
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}
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std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
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int width_a = GetSize(a);
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int width_b = GetSize(b);
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std::vector<DepthSig> products;
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products.reserve(width_a + 3);
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for (int i = 0; i < width_a; i++) {
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SigBit ai = a[i];
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// b_shifted = (0_i ## b)
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SigSpec b_shifted = SigSpec(State::S0, i);
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b_shifted.append(b);
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b_shifted = normalize_to_width(b_shifted, false, width);
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// row = b_shifted & replicate(a[i], width)
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SigSpec ai_rep = SigSpec(ai, width);
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SigSpec row = module->addWire(NEW_ID, width);
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module->addAnd(NEW_ID, b_shifted, ai_rep, row);
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// Apply Modified Baugh-Wooley inversions for this row
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bool row_is_bottom = (i == width_a - 1);
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bool any_inversion = (row_is_bottom && b_signed) || a_signed;
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if (any_inversion) {
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std::vector<RTLIL::State> mask(width, RTLIL::State::S0);
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for (int j = 0; j < width_b; j++) {
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int col = i + j;
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if (col < 0 || col >= width)
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continue;
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bool col_is_right = (j == width_b - 1);
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// Flip masks
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bool invert = (row_is_bottom && b_signed) ^ (col_is_right && a_signed);
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if (invert)
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mask[col] = RTLIL::State::S1;
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}
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// Skip the xor entirely if the mask is all zeroes
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bool nonzero = false;
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for (auto s : mask)
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if (s == RTLIL::State::S1) {
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nonzero = true;
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break;
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}
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if (nonzero) {
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SigSpec inverted = module->addWire(NEW_ID, width);
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module->addXor(NEW_ID, row, SigSpec(RTLIL::Const(mask)), inverted);
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row = inverted;
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}
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}
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products.push_back({row, 0});
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}
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// Correction constants
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auto push_one_at = [&](int col) {
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if (col < 0 || col >= width)
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return;
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std::vector<RTLIL::State> v(width, RTLIL::State::S0);
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v[col] = RTLIL::State::S1;
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products.push_back({SigSpec(RTLIL::Const(v)), 0});
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};
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if (b_signed)
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push_one_at(width_a - 1);
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if (a_signed)
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push_one_at(width_b - 1);
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if (a_signed || b_signed)
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push_one_at(width_a + width_b - 1);
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return products;
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}
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std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count) {
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int levels = 0;
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int fa_count = 0;
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int c42_count = 0;
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int final_depth = 0;
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for (auto &op : operands)
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op.sig.extend_u0(width);
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// Only compress operands ready at current level
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for (int level = 0; operands.size() > 2; level++) {
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// Partition operands into ready and waiting
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std::vector<DepthSig> ready;
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std::vector<DepthSig> waiting;
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ready.reserve(operands.size());
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for (auto &op : operands) {
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if (op.depth <= level)
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ready.push_back(op);
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else
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waiting.push_back(op);
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}
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if (ready.size() < 3) {
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levels++;
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continue;
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}
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// Apply compressors to ready operands
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std::vector<DepthSig> compressed;
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compressed.reserve(ready.size());
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size_t i = 0;
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// PREFER_42 attempts 4:2 grouping greedily (falls back to 3:2 for the residual)
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// FA_ONLY skips
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// DADDA = PREFER_42 (TODO: inspect column heights?)
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bool try_42 = (strategy == Strategy::PREFER_42 || strategy == Strategy::DADDA);
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while (i < ready.size()) {
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size_t remaining = ready.size() - i;
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if (try_42 && remaining >= 4) {
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DepthSig a = ready[i + 0];
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DepthSig b = ready[i + 1];
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DepthSig c = ready[i + 2];
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DepthSig d = ready[i + 3];
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auto [sum, carry] = emit_compressor_42(module, a.sig, b.sig, c.sig, d.sig, width);
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int dmax = std::max({a.depth, a.depth, a.depth, a.depth});
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compressed.push_back({sum, dmax + 2});
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compressed.push_back({carry, dmax + 2});
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fa_count += 2;
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c42_count += 1;
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i += 4;
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} else if (remaining >= 3) {
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DepthSig a = ready[i + 0];
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DepthSig b = ready[i + 1];
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DepthSig c = ready[i + 2];
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auto [sum, carry] = emit_compressor_32(module, a.sig, b.sig, c.sig, width);
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int dmax = std::max({a.depth, b.depth, c.depth});
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compressed.push_back({sum, dmax + 1});
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compressed.push_back({carry, dmax + 1});
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fa_count += 1;
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i += 3;
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} else {
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// Uncompressed operands pass through to next level
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for (; i < ready.size(); i++)
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compressed.push_back(ready[i]);
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break;
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}
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}
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// Merge compressed with waiting operands
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for (auto &op : waiting)
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compressed.push_back(op);
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operands = std::move(compressed);
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levels++;
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}
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if(compressor_count)
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*compressor_count = fa_count;
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if (operands.size() == 0)
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return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
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if (operands.size() == 1)
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return {operands[0].sig, SigSpec(State::S0, width)};
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final_depth = std::max(operands[0].depth, operands[1].depth);
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log_assert(operands.size() == 2);
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log(" CompressorTree::reduce_scheduled: %d levels, %d $fa (%d as 4:2), final depth %d\n", levels, fa_count, c42_count, final_depth);
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return {operands[0].sig, operands[1].sig};
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}
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void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
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{
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int width = GetSize(y);
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log_assert(GetSize(a) == width);
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log_assert(GetSize(b) == width);
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if (width == 0)
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return;
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if (width == 1) {
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module->addXorGate(NEW_ID, a[0], b[0], y[0]);
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return;
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}
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// Bit level gen and prop
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std::vector<SigBit> g_pre(width), p_pre(width);
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for (int i = 0; i < width; i++) {
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SigBit gi = module->addWire(NEW_ID);
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SigBit pi = module->addWire(NEW_ID);
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module->addAndGate(NEW_ID, a[i], b[i], gi);
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module->addXorGate(NEW_ID, a[i], b[i], pi);
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g_pre[i] = gi;
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p_pre[i] = pi;
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}
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// Propagate (g, p) through ceil(log2 W) levels
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std::vector<SigBit> g = g_pre;
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std::vector<SigBit> p = p_pre;
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int num_levels = 0;
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while ((1 << num_levels) < width)
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num_levels++;
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for (int k = 1; k <= num_levels; k++) {
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int s = 1 << (k - 1);
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std::vector<SigBit> g_next(width), p_next(width);
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for (int i = 0; i < width; i++) {
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if (i < s) {
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// Nothing to do
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g_next[i] = g[i];
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p_next[i] = p[i];
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} else {
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// g_i^k = g_i | (p_i & g_(i-s))
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SigBit and_pg = module->addWire(NEW_ID);
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module->addAndGate(NEW_ID, p[i], g[i - s], and_pg);
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SigBit gnew = module->addWire(NEW_ID);
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module->addOrGate(NEW_ID, g[i], and_pg, gnew);
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g_next[i] = gnew;
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// p_i^k = p_i & p_(i-s)
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if (k < num_levels) {
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SigBit pnew = module->addWire(NEW_ID);
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module->addAndGate(NEW_ID, p[i], p[i - s], pnew);
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p_next[i] = pnew;
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} else {
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// Skip last level
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p_next[i] = State::Sx;
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}
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}
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}
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g = std::move(g_next);
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p = std::move(p_next);
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}
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// Sum layer, g[i] is COUT of bit i
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// With CIN 0:
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// sum[0] = p_pre[0]
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// sum[i] = p_pre[i] ^ g[i-1] ...
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module->connect(y[0], p_pre[0]);
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for (int i = 1; i < width; i++)
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module->addXorGate(NEW_ID, p_pre[i], g[i - 1], y[i]);
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}
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Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice) {
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switch (choice) {
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case FinalAdder::DEFAULT:
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case FinalAdder::RIPPLE: {
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return module->addAdd(NEW_ID, a, b, y, false);
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}
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case FinalAdder::PARALLEL_PREFIX: {
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emit_kogge_stone(module, a, b, y);
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return nullptr;
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}
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}
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log_assert(false && "CompressorTree::emit_final_adder: invalid choice");
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return nullptr;
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}
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FinalAdder pick_final_adder(int width, FinalMode mode) {
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switch (mode) {
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case FinalMode::RIPPLE: return FinalAdder::RIPPLE;
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case FinalMode::PREFIX: return FinalAdder::PARALLEL_PREFIX;
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case FinalMode::AUTO:
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default: return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
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}
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}
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} // namespace CompressorTree
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YOSYS_NAMESPACE_END
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@ -55,60 +55,10 @@ enum class FinalMode {
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PREFIX,
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};
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inline std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
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{
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec cout = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, a, b, c, cout, sum);
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std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
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std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
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SigSpec carry;
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carry.append(State::S0);
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carry.append(cout.extract(0, width - 1));
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return {sum, carry};
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}
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inline std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width)
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{
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// First FA: a + b + c -> s0
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SigSpec s0 = module->addWire(NEW_ID, width);
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SigSpec cout_h_full = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, a, b, c, cout_h_full, s0);
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// cin[0] = 0, cin[i] = cout_h_full[i-1]
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SigSpec cin;
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cin.append(State::S0);
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if (width > 1)
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cin.append(cout_h_full.extract(0, width - 1));
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// Second FA: s0 + d + cin -> sum
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SigSpec sum = module->addWire(NEW_ID, width);
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SigSpec carry_full = module->addWire(NEW_ID, width);
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module->addFa(NEW_ID, s0, d, cin, carry_full, sum);
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SigSpec carry;
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carry.append(State::S0);
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if (width > 1)
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carry.append(carry_full.extract(0, width - 1));
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return {sum, carry};
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}
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inline SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
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{
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// Zero/sign-extend to width
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if (GetSize(sig) < width) {
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SigBit pad;
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if (is_signed && GetSize(sig) > 0)
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pad = sig[GetSize(sig) - 1];
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else
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pad = State::S0;
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sig.append(SigSpec(pad, width - GetSize(sig)));
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}
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// Truncate to width
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if (GetSize(sig) > width)
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sig = sig.extract(0, width);
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return sig;
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}
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SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width);
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/**
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* generate_partial_products() - Generate partial products for FMA concat
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@ -121,78 +71,7 @@ inline SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
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*
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* Return: Partial-product matrix as a set of depth-0 vectors
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*/
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inline std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
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int width_a = GetSize(a);
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int width_b = GetSize(b);
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std::vector<DepthSig> products;
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products.reserve(width_a + 3);
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for (int i = 0; i < width_a; i++) {
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SigBit ai = a[i];
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// b_shifted = (0_i ## b)
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SigSpec b_shifted = SigSpec(State::S0, i);
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b_shifted.append(b);
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b_shifted = normalize_to_width(b_shifted, false, width);
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// row = b_shifted & replicate(a[i], width)
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SigSpec ai_rep = SigSpec(ai, width);
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SigSpec row = module->addWire(NEW_ID, width);
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module->addAnd(NEW_ID, b_shifted, ai_rep, row);
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// Apply Modified Baugh-Wooley inversions for this row
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bool row_is_bottom = (i == width_a - 1);
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bool any_inversion = (row_is_bottom && b_signed) || a_signed;
|
||||
|
||||
if (any_inversion) {
|
||||
std::vector<RTLIL::State> mask(width, RTLIL::State::S0);
|
||||
|
||||
for (int j = 0; j < width_b; j++) {
|
||||
int col = i + j;
|
||||
if (col < 0 || col >= width)
|
||||
continue;
|
||||
bool col_is_right = (j == width_b - 1);
|
||||
// Flip masks
|
||||
bool invert = (row_is_bottom && b_signed) ^ (col_is_right && a_signed);
|
||||
if (invert)
|
||||
mask[col] = RTLIL::State::S1;
|
||||
}
|
||||
|
||||
// Skip the xor entirely if the mask is all zeroes
|
||||
bool nonzero = false;
|
||||
for (auto s : mask)
|
||||
if (s == RTLIL::State::S1) {
|
||||
nonzero = true;
|
||||
break;
|
||||
}
|
||||
if (nonzero) {
|
||||
SigSpec inverted = module->addWire(NEW_ID, width);
|
||||
module->addXor(NEW_ID, row, SigSpec(RTLIL::Const(mask)), inverted);
|
||||
row = inverted;
|
||||
}
|
||||
}
|
||||
|
||||
products.push_back({row, 0});
|
||||
}
|
||||
|
||||
// Correction constants
|
||||
auto push_one_at = [&](int col) {
|
||||
if (col < 0 || col >= width)
|
||||
return;
|
||||
std::vector<RTLIL::State> v(width, RTLIL::State::S0);
|
||||
v[col] = RTLIL::State::S1;
|
||||
products.push_back({SigSpec(RTLIL::Const(v)), 0});
|
||||
};
|
||||
|
||||
if (b_signed)
|
||||
push_one_at(width_a - 1);
|
||||
if (a_signed)
|
||||
push_one_at(width_b - 1);
|
||||
if (a_signed || b_signed)
|
||||
push_one_at(width_a + width_b - 1);
|
||||
|
||||
return products;
|
||||
}
|
||||
std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width);
|
||||
|
||||
/**
|
||||
* reduce_scheduled() - Reduce multiple operands to two using a compressor tree
|
||||
|
|
@ -205,103 +84,7 @@ inline std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a
|
|||
*
|
||||
* Return: The final two reduced operands, that are to be fed into an adder
|
||||
*/
|
||||
inline std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count = nullptr) {
|
||||
int levels = 0;
|
||||
int fa_count = 0;
|
||||
int c42_count = 0;
|
||||
int final_depth = 0;
|
||||
|
||||
for (auto &op : operands)
|
||||
op.sig.extend_u0(width);
|
||||
|
||||
// Only compress operands ready at current level
|
||||
for (int level = 0; operands.size() > 2; level++) {
|
||||
// Partition operands into ready and waiting
|
||||
std::vector<DepthSig> ready;
|
||||
std::vector<DepthSig> waiting;
|
||||
ready.reserve(operands.size());
|
||||
for (auto &op : operands) {
|
||||
if (op.depth <= level)
|
||||
ready.push_back(op);
|
||||
else
|
||||
waiting.push_back(op);
|
||||
}
|
||||
|
||||
if (ready.size() < 3) {
|
||||
levels++;
|
||||
continue;
|
||||
}
|
||||
|
||||
// Apply compressors to ready operands
|
||||
std::vector<DepthSig> compressed;
|
||||
compressed.reserve(ready.size());
|
||||
size_t i = 0;
|
||||
|
||||
// PREFER_42 attempts 4:2 grouping greedily (falls back to 3:2 for the residual)
|
||||
// FA_ONLY skips
|
||||
// DADDA = PREFER_42 (TODO: inspect column heights?)
|
||||
bool try_42 = (strategy == Strategy::PREFER_42 || strategy == Strategy::DADDA);
|
||||
|
||||
while (i < ready.size()) {
|
||||
size_t remaining = ready.size() - i;
|
||||
|
||||
if (try_42 && remaining >= 4) {
|
||||
DepthSig a = ready[i + 0];
|
||||
DepthSig b = ready[i + 1];
|
||||
DepthSig c = ready[i + 2];
|
||||
DepthSig d = ready[i + 3];
|
||||
|
||||
auto [sum, carry] = emit_compressor_42(module, a.sig, b.sig, c.sig, d.sig, width);
|
||||
int dmax = std::max({a.depth, a.depth, a.depth, a.depth});
|
||||
|
||||
compressed.push_back({sum, dmax + 2});
|
||||
compressed.push_back({carry, dmax + 2});
|
||||
|
||||
fa_count += 2;
|
||||
c42_count += 1;
|
||||
i += 4;
|
||||
} else if (remaining >= 3) {
|
||||
DepthSig a = ready[i + 0];
|
||||
DepthSig b = ready[i + 1];
|
||||
DepthSig c = ready[i + 2];
|
||||
|
||||
auto [sum, carry] = emit_compressor_32(module, a.sig, b.sig, c.sig, width);
|
||||
int dmax = std::max({a.depth, b.depth, c.depth});
|
||||
|
||||
compressed.push_back({sum, dmax + 1});
|
||||
compressed.push_back({carry, dmax + 1});
|
||||
|
||||
fa_count += 1;
|
||||
i += 3;
|
||||
} else {
|
||||
// Uncompressed operands pass through to next level
|
||||
for (; i < ready.size(); i++)
|
||||
compressed.push_back(ready[i]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Merge compressed with waiting operands
|
||||
for (auto &op : waiting)
|
||||
compressed.push_back(op);
|
||||
|
||||
operands = std::move(compressed);
|
||||
levels++;
|
||||
}
|
||||
|
||||
if(compressor_count)
|
||||
*compressor_count = fa_count;
|
||||
|
||||
if (operands.size() == 0)
|
||||
return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
|
||||
if (operands.size() == 1)
|
||||
return {operands[0].sig, SigSpec(State::S0, width)};
|
||||
|
||||
final_depth = std::max(operands[0].depth, operands[1].depth);
|
||||
log_assert(operands.size() == 2);
|
||||
log(" CompressorTree::reduce_scheduled: %d levels, %d $fa (%d as 4:2), final depth %d\n", levels, fa_count, c42_count, final_depth);
|
||||
return {operands[0].sig, operands[1].sig};
|
||||
}
|
||||
std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count = nullptr);
|
||||
|
||||
/**
|
||||
* emit_kogge_stone() - Emit a Kogge-Stone parallel-prefix adder
|
||||
|
|
@ -310,79 +93,7 @@ inline std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<
|
|||
* @b: Signal B
|
||||
* @y: Signal Y = (A + B) mod 2^W
|
||||
*/
|
||||
inline void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
|
||||
{
|
||||
int width = GetSize(y);
|
||||
log_assert(GetSize(a) == width);
|
||||
log_assert(GetSize(b) == width);
|
||||
|
||||
if (width == 0)
|
||||
return;
|
||||
|
||||
if (width == 1) {
|
||||
module->addXorGate(NEW_ID, a[0], b[0], y[0]);
|
||||
return;
|
||||
}
|
||||
|
||||
// Bit level gen and prop
|
||||
std::vector<SigBit> g_pre(width), p_pre(width);
|
||||
for (int i = 0; i < width; i++) {
|
||||
SigBit gi = module->addWire(NEW_ID);
|
||||
SigBit pi = module->addWire(NEW_ID);
|
||||
module->addAndGate(NEW_ID, a[i], b[i], gi);
|
||||
module->addXorGate(NEW_ID, a[i], b[i], pi);
|
||||
g_pre[i] = gi;
|
||||
p_pre[i] = pi;
|
||||
}
|
||||
|
||||
// Propagate (g, p) through ceil(log2 W) levels
|
||||
std::vector<SigBit> g = g_pre;
|
||||
std::vector<SigBit> p = p_pre;
|
||||
int num_levels = 0;
|
||||
|
||||
while ((1 << num_levels) < width)
|
||||
num_levels++;
|
||||
|
||||
for (int k = 1; k <= num_levels; k++) {
|
||||
int s = 1 << (k - 1);
|
||||
std::vector<SigBit> g_next(width), p_next(width);
|
||||
for (int i = 0; i < width; i++) {
|
||||
if (i < s) {
|
||||
// Nothing to do
|
||||
g_next[i] = g[i];
|
||||
p_next[i] = p[i];
|
||||
} else {
|
||||
// g_i^k = g_i | (p_i & g_(i-s))
|
||||
SigBit and_pg = module->addWire(NEW_ID);
|
||||
module->addAndGate(NEW_ID, p[i], g[i - s], and_pg);
|
||||
SigBit gnew = module->addWire(NEW_ID);
|
||||
module->addOrGate(NEW_ID, g[i], and_pg, gnew);
|
||||
g_next[i] = gnew;
|
||||
|
||||
// p_i^k = p_i & p_(i-s)
|
||||
if (k < num_levels) {
|
||||
SigBit pnew = module->addWire(NEW_ID);
|
||||
module->addAndGate(NEW_ID, p[i], p[i - s], pnew);
|
||||
p_next[i] = pnew;
|
||||
} else {
|
||||
// Skip last level
|
||||
p_next[i] = State::Sx;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
g = std::move(g_next);
|
||||
p = std::move(p_next);
|
||||
}
|
||||
|
||||
// Sum layer, g[i] is COUT of bit i
|
||||
// With CIN 0:
|
||||
// sum[0] = p_pre[0]
|
||||
// sum[i] = p_pre[i] ^ g[i-1] ...
|
||||
module->connect(y[0], p_pre[0]);
|
||||
for (int i = 1; i < width; i++)
|
||||
module->addXorGate(NEW_ID, p_pre[i], g[i - 1], y[i]);
|
||||
}
|
||||
void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y);
|
||||
|
||||
/**
|
||||
* emit_final_adder() - Emit the final carry-propagate addition between the two reduced vectors
|
||||
|
|
@ -394,29 +105,9 @@ inline void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
|
|||
*
|
||||
* Return: Cell* of the emitted instance
|
||||
*/
|
||||
inline Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice) {
|
||||
switch (choice) {
|
||||
case FinalAdder::DEFAULT:
|
||||
case FinalAdder::RIPPLE: {
|
||||
return module->addAdd(NEW_ID, a, b, y, false);
|
||||
}
|
||||
case FinalAdder::PARALLEL_PREFIX: {
|
||||
emit_kogge_stone(module, a, b, y);
|
||||
return nullptr;
|
||||
}
|
||||
}
|
||||
log_assert(false && "CompressorTree::emit_final_adder: invalid choice");
|
||||
return nullptr;
|
||||
}
|
||||
Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice);
|
||||
|
||||
inline FinalAdder pick_final_adder(int width, FinalMode mode) {
|
||||
switch (mode) {
|
||||
case FinalMode::RIPPLE: return FinalAdder::RIPPLE;
|
||||
case FinalMode::PREFIX: return FinalAdder::PARALLEL_PREFIX;
|
||||
case FinalMode::AUTO:
|
||||
default: return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
|
||||
}
|
||||
}
|
||||
FinalAdder pick_final_adder(int width, FinalMode mode);
|
||||
|
||||
} // namespace CompressorTree
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue