mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-23 21:09:14 +00:00
7 lines
107 B
Verilog
7 lines
107 B
Verilog
module add_with_const(
|
|
input [7:0] a, b, c,
|
|
output [7:0] y
|
|
);
|
|
assign y = a + b + c + 8'd42;
|
|
endmodule
|
|
|