..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v
Fixed typo in tests/simple/arraycells.v
2017-01-04 12:39:01 +01:00
arrays01.v
arrays02.sv
Add proper test for SV-style arrays
2019-06-20 12:06:07 +02:00
attrib01_module.v
Added tests for attributes
2019-06-03 09:25:20 +02:00
attrib02_port_decl.v
Added tests for attributes
2019-06-03 09:25:20 +02:00
attrib03_parameter.v
Added tests for attributes
2019-06-03 09:25:20 +02:00
attrib04_net_var.v
Added tests for attributes
2019-06-03 09:25:20 +02:00
attrib05_port_conn.v.DISABLED
Added tests for attributes
2019-06-03 09:25:20 +02:00
attrib06_operator_suffix.v
Added tests for attributes
2019-06-03 09:25:20 +02:00
attrib07_func_call.v.DISABLED
Added tests for attributes
2019-06-03 09:25:20 +02:00
attrib08_mod_inst.v
Added tests for attributes
2019-06-03 09:25:20 +02:00
attrib09_case.v
Added tests for attributes
2019-06-03 09:25:20 +02:00
carryadd.v
constmuldivmod.v
Added opt_expr support for div/mod by power-of-two
2016-05-29 12:17:36 +02:00
constpower.v
defvalue.sv
Add defvalue test, minor autotest fixes for .sv files
2019-06-19 12:12:08 +02:00
dff_different_styles.v
dff_init.v
Add test case from #997
2019-05-07 19:58:04 +02:00
fiedler-cooley.v
forgen01.v
forgen02.v
forloops.v
Add additional test cases for for-loops
2019-05-01 09:32:07 +02:00
fsm.v
generate.v
Add test
2019-06-20 16:07:22 -07:00
graphtest.v
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
hierarchy.v
hierdefparam.v
Fix handling of defparam for when default_nettype is none
2019-02-24 20:09:41 +01:00
i2c_master_tests.v
implicit_ports.v
Rename implicit_ports.sv test to implicit_ports.v
2019-06-07 13:12:25 +02:00
localparam_attr.v
Added tests for Verilog frontent for attributes on parameters and localparams
2019-05-16 12:53:43 +02:00
loops.v
macros.v
mem2reg.v
Add splitcmplxassign test case and silence splitcmplxassign warning
2019-05-01 10:01:54 +02:00
mem_arst.v
memory.v
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
multiplier.v
muxtree.v
omsp_dbg_uart.v
operators.v
param_attr.v
Added tests for Verilog frontent for attributes on parameters and localparams
2019-05-16 12:53:43 +02:00
paramods.v
partsel.v
peepopt.v
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
2019-05-28 17:17:56 +02:00
process.v
realexpr.v
repwhile.v
retime.v
Add retime test
2019-04-05 16:28:46 -07:00
rotate.v
run-test.sh
SystemVerilog support for implicit named port connections
2019-06-06 18:07:49 +02:00
scopes.v
signedexpr.v
sincos.v
specify.v
Fix tests/simple/specify.v
2018-03-27 14:34:00 +02:00
subbytes.v
task_func.v
Fix handling of task output ports in clocked always blocks, fixes #857
2019-03-07 22:44:37 -08:00
undef_eqx_nex.v
usb_phy_tests.v
values.v
vloghammer.v
wandwor.v
Add actual wandwor test that is part of "make test"
2019-05-28 16:42:50 +02:00
wreduce.v
xfirrtl
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
2019-07-31 09:27:38 -07:00
3b8c917025